Patents by Inventor Bryan S. Rosenburg
Bryan S. Rosenburg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160363916Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Bryan S. Rosenburg
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Publication number: 20160301428Abstract: A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.Type: ApplicationFiled: April 11, 2015Publication date: October 13, 2016Inventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Patent number: 9317350Abstract: A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.Type: GrantFiled: September 9, 2013Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Chen-Yong Cher, Carlos H. Andrade Costa, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Patent number: 9298553Abstract: A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.Type: GrantFiled: February 8, 2014Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Publication number: 20160085640Abstract: A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Publication number: 20160042280Abstract: A method for managing a network queue memory includes receiving sensor information about the network queue memory, predicting a memory failure in the network queue memory based on the sensor information, and outputting a notification through a plurality of nodes forming a network and using the network queue memory, the notification configuring communications between the nodes.Type: ApplicationFiled: August 7, 2014Publication date: February 11, 2016Inventors: CARLOS H. ANDRADE COSTA, CHEN-YONG CHER, YOONHO PARK, BRYAN S. ROSENBURG, KYUNG D. RYU
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Patent number: 9146609Abstract: According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.Type: GrantFiled: November 20, 2012Date of Patent: September 29, 2015Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Bryan S. Rosenburg, Kyung D. Ryu, Augusto J. Vega
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Patent number: 9141173Abstract: According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.Type: GrantFiled: August 15, 2013Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Bryan S. Rosenburg, Kyung D. Ryu, Augusto J. Vega
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Publication number: 20150227426Abstract: A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.Type: ApplicationFiled: February 8, 2014Publication date: August 13, 2015Applicant: International Business Machines CorporationInventors: Carlos H. Andrade Costa, Chen-Yong Cher, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Publication number: 20150074367Abstract: A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.Type: ApplicationFiled: September 9, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Chen-Yong Cher, Carlos H. Andrade Costa, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Publication number: 20150074469Abstract: A method for providing notification of a predictable memory failure includes the steps of: obtaining information regarding at least one condition associated with a memory; calculating a memory failure probability as a function of the obtained information; calculating a failure probability threshold; and generating a signal when the memory failure probability exceeds the failure probability threshold, the signal being indicative of a predicted future memory failure.Type: ApplicationFiled: September 9, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Chen-Yong Cher, Carlos H. Andrade Costa, Yoonho Park, Bryan S. Rosenburg, Kyung D. Ryu
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Patent number: 8918799Abstract: A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system.Type: GrantFiled: March 30, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Todd A. Inglett, Yoonho Park, Bryan S. Rosenburg, Robert W. Wisniewski
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Patent number: 8869153Abstract: A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.Type: GrantFiled: May 30, 2008Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Orran Y. Krieger, Bryan S. Rosenburg, Robert B. Tremaine, Robert W. Wisniewski
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Patent number: 8789046Abstract: Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application.Type: GrantFiled: March 30, 2012Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Hubertus Franke, Todd A. Inglett, Yoonho Park, Hartmut Penner, Bryan S. Rosenburg, Robert W. Wisniewski
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Publication number: 20140143783Abstract: According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Bryan S. Rosenburg, Kyung D. Ryu, Augusto J. Vega
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Publication number: 20140143570Abstract: According to one embodiment, a method for thread consolidation is provided for a system that includes an operating system and a multi-core processing chip in communication with an accelerator chip. The method includes running an application having software threads on the operating system, mapping the software threads to physical cores in the multi-core processing chip, identifying one or more idle hardware threads in the multi-core processing chip and identifying one or more idle accelerator units in the accelerator chip. The method also includes executing the software threads on the physical cores and the accelerator unit. The method also includes the controller module consolidating the software threads executing on the physical cores, resulting in one or more idle physical cores and a consolidated physical core. The method also includes the controller module activating a power savings mode for the one or more idle physical cores.Type: ApplicationFiled: August 15, 2013Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Bryan S. Rosenburg, Kyung D. Ryu, Augusto J. Vega
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Publication number: 20130263121Abstract: Enabling a Light-Weight Kernel (LWK) to run in a virtualized environment on a Full-Weight Kernel (FWK), in one aspect, may include replacing a FWK loader, e.g., FWK's dynamic library loader or linker, with a LWK library on a first computing entity for an application allocated to run on one or more second computing entities. The LWK library may be enabled to initialize the one or more second computing entities and associated memory allocated to run the application under the LWK library. The LWK library may be enabled to manage the one or more second computing entities and said associated memory and resources needed by the application.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: International Business Machines CorporationInventors: Hubertus Franke, Todd A. Inglett, Yoonho Park, Hartmut Penner, Bryan S. Rosenburg, Robert W. Wisniewski
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Publication number: 20130263157Abstract: A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd A. Inglett, Yoonho Park, Bryan S. Rosenburg, Robert W. Wisniewski
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Patent number: 8495649Abstract: A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information.Type: GrantFiled: July 19, 2006Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Orran Y. Krieger, Bryan S. Rosenburg, Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski
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Patent number: 8051276Abstract: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.Type: GrantFiled: July 7, 2006Date of Patent: November 1, 2011Assignee: International Business Machines CorporationInventors: Orran Y. Krieger, Bryan S. Rosenburg, Robert B. Tremaine, Robert W. Wisniewski