Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses to determine transmission equalization coefficients (TxEQs) for one or more lanes of a high speed serial link. Embodiments include determining a jitter tolerance for each TxEQ of a plurality of TxEQs for a lane of the link. The jitter tolerance for each TxEQ for the lane is based on a level of jitter induced on the lane to detect a number of errors on the lane; determining a voltage (VOC) margin for each TxEQ for the lane, wherein the voltage margin for the lane is based on a voltage corners test applied to the lane to detect a number of errors on the lane at a high voltage point and a low voltage point; determining a TxEQ that provides maximum jitter tolerance and based on the determined lowest voltage margin; and using the TxEQ for the lane during operation.

Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes a scheduler to schedule memory transactions to the DIMM and a write address queue to accumulate the write requests while the memory controller is operating in a first mode and to release the write requests to the scheduler whenever the memory controller is operating in a second mode.

Abstract: A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.

Abstract: An arrangement is provided for efficiently enforcing global ordering in a computing system using an inter-queue ordering mechanism (IQOM). The IQOM may be located in a bridge (e.g., a caching bridge) coupling two interconnects: an internal interconnect to connect different processing units (e.g., processing cores inside a processor or a single core processor) and a system interconnect to connect different processors and/or different internal interconnects. The bridge handles transactions from two directions: inbound—from the system interconnect to an internal interconnect, and outbound—from an internal interconnect to the system interconnect. The IQOM may be used to enforce strict ordering among inbound transactions and among outbound transactions separately and thus allow certain inbound transactions that occur on the system interconnect after an outbound transaction to be completed before the outbound transaction.

Abstract: A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.