Patents by Inventor Bryan Theodore Silbermann

Bryan Theodore Silbermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11544207
    Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Paul Stonelake, Bryan Theodore Silbermann, Frank F. Ross
  • Publication number: 20210271617
    Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Paul Stonelake, Bryan Theodore Silbermann, Frank F. Ross
  • Publication number: 20100244785
    Abstract: Methods and systems for charging energy storage devices are disclosed. Often the charging circuit may have different levels of power available to charge the energy storage device depending on the state of other subsystems of the electronic system. The present invention provides a source power limiting charging system. Often the losses of the charging system and losses due to the power requirements of support systems are not well known and/or are variable. Controlling source power to the charging system maximizes the amount of power delivered to the energy storage device for a given value of these losses and avoids power contention with the other elements of the electronic system. Therefore, the power drawn from the power source by a controllable power limiting charging circuit is controlled to be less than a source power limit.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 30, 2010
    Applicant: Applied Micro Circuits Corporation
    Inventors: Bryan Theodore Silbermann, Thomas Joel Huber