Abstract: When an NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine (i.e., an original secondary code sequence), a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the NEW SECONDARY CODE EXECUTION START POINT signal. The new secondary program code start point sync marker identifies the absolute program counter address at the time of the generation of the NEW SECONDARY CODE EXECUTION START POINT signal and relates the NEW SECONDARY CODE EXECUTION START POINT signal sync marker to a timing trace stream. The NEW SECONDARY CODE EXECUTION START POINT signal is generated after the instructions from the original secondary code sequence are removed from the pipeline flattener and the first new secondary code instruction is removed from the pipeline flattener.

Abstract: A PAUSE POINT signal is generated in a target processor when execution of an original code sequence is to be terminated and a new code sequence is to be executed. A pause point sync marker is generated in a program counter trace stream as a result of the PAUSE POINT signal. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the PAUSE POINT signal. The pause point sync marker identifies the program counter address at the time of the generation of the PAUSE POINT signal and relates the PAUSE POINT signal to a timing trace stream. The PAUSE POINT signal is generated during a pause in the processor instruction execution while instructions from the original code sequence are stored in the pipeline flattener and before the new code instructions have been entered in the pipeline flattener.

Abstract: When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected events and relates the occurrence of these events to timing trace stream. The sync marker for the plurality of preselected events differs from a single event sync marker by including at least one additional packet. The additional packet includes logic signals stored at locations related to each identified event.

Abstract: In a test and debug system, information is transmitted from the target processor to the host processor in groups of packets that can include one or more packets. The packets include an extension portion and a payload portion. Because the packets have relatively small number of logic signals, the extension portions can be used to determine, based on header information, the number of packet sub-group and the number of packets in each packet subgroup.

Abstract: When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal. The interrupt service routine code flush sync marker identifies the absolute program counter address at the time of the generation of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal and relates the INTERRUPT SERVICE ROUTINE CODE FLUSH signal sync marker to a timing trace stream. The INTERRUPT SERVICE ROUTINE CODE FLUSH signal is generated at the transition between the interrupt service routine (secondary) code instructions being removed from the pipeline flattener and the program (primary) code instructions being removed from the pipeline flattener.

Abstract: When a PROGRAM CODE START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the PROGRAM CODE START POINT signal. The program code start point sync marker identifies the absolute program counter address at the time of the generation of the PROGRAM CODE START POINT signal and relates the PROGRAM CODE START POINT signal sync marker to a timing trace stream. The PROGRAM CODE START POINT signal is generated after the instructions are removed from the pipeline flattener and the first program (primary) code instruction is removed from the pipeline flattener. The PROGRAM CODE START POINT signal sync marker alerts the host processor to the initiation and context of the program code execution.

Abstract: When a PROGRAM CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the PROGRAM CODE FLUSH signal. The program code flush sync marker identifies the absolute program counter address at the time of the generation of the PROGRAM CODE FLUSH signal and relates the PROGRAM CODE FLUSH signal sync marker to a timing trace stream. The PROGRAM CODE FLUSH signal is generated at the transition between the program (primary) code instructions being removed from the pipeline flattener and the interrupt service routine (secondary) code instructions being removed from the pipeline flattener.

Abstract: When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The debug halt sync marker includes a plurality of packets, the packets identifying that the sync marker is the result of a DEBUG HALT signal. The packets also identify the program counter address at the time of the generation of the DEBUG HALT signal and relate the debug halt sync marker to a timing trace stream.

Abstract: A method of tracing activity of a data processor includes collecting and transmitting trace data. An epause marker is embedded in the trace stream upon detection of an emulation halt. This epause marker includes a little offset indicating a number of latency instructions within trace collection hardware since a program counter exception. This permits the utilization emulation device to annulling trace data corresponding to the latency instructions.

Abstract: Trace data compression includes selectively transmitting data packets, data addresses and program counter addresses and transmitting which are transmitted in a data log header. Trace data compression further includes determining and not transmitting most significant bytes of data, data address or program counter address having bits that all equal the most significant bit. This requires an indication of the data, data address and program counter address length. Trace data compression further includes transmitting only bytes of data, data address and program counter address which differ from corresponding byte of the prior data, data address and program counter address together with a map indicating which bytes are transmitted.