Patents by Inventor Bryan Wayne Pogor
Bryan Wayne Pogor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8909908Abstract: A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.Type: GrantFiled: October 21, 2009Date of Patent: December 9, 2014Assignee: VIA Technologies, Inc.Inventors: Rodney E. Hooker, Gerard M. Col, Bryan Wayne Pogor
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Patent number: 8539209Abstract: A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.Type: GrantFiled: October 28, 2009Date of Patent: September 17, 2013Assignee: VIA Technologies, Inc.Inventors: Bryan Wayne Pogor, Colin Eddy
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Patent number: 8332618Abstract: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.Type: GrantFiled: December 9, 2009Date of Patent: December 11, 2012Assignee: VIA Technologies, Inc.Inventors: Gerard M. Col, Matthew Daniel Day, Terry Parks, Bryan Wayne Pogor
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Patent number: 8327119Abstract: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector.Type: GrantFiled: October 21, 2009Date of Patent: December 4, 2012Assignee: VIA Technologies, Inc.Inventor: Bryan Wayne Pogor
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Patent number: 8074060Abstract: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result.Type: GrantFiled: November 25, 2008Date of Patent: December 6, 2011Assignee: VIA Technologies, Inc.Inventors: Gerard M. Col, Brent Bean, Bryan Wayne Pogor
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Publication number: 20110047314Abstract: A microprocessor breakpoint checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.Type: ApplicationFiled: October 28, 2009Publication date: February 24, 2011Applicant: VIA Technologies, Inc.Inventors: Bryan Wayne Pogor, Colin Eddy
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Publication number: 20110035573Abstract: An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.Type: ApplicationFiled: December 9, 2009Publication date: February 10, 2011Applicant: VIA Technologies, Inc.Inventors: Gerard M. Col, Matthew Daniel Day, Terry Parks, Bryan Wayne Pogor
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Publication number: 20110016296Abstract: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector.Type: ApplicationFiled: October 21, 2009Publication date: January 20, 2011Applicant: VIA Technologies, IncInventor: Bryan Wayne Pogor
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Publication number: 20100306506Abstract: A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.Type: ApplicationFiled: October 21, 2009Publication date: December 2, 2010Applicant: VIA Technologies, Inc.Inventors: Rodney E. Hooker, Gerard M. Col, Bryan Wayne Pogor
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Publication number: 20100131742Abstract: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result.Type: ApplicationFiled: November 25, 2008Publication date: May 27, 2010Applicant: VIA Technologies, Inc.Inventors: Gerard M. Col, Brent Bean, Bryan Wayne Pogor
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Patent number: 6748458Abstract: The input/output expansion system (“I/O expansion system”) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.Type: GrantFiled: August 31, 2001Date of Patent: June 8, 2004Assignee: Hewlett Packard Development Company, L.P.Inventors: J. Michael Andrewartha, Martha G. Peterson, Farrukh S. Syed, Brent A. Boudreaux, Richard A. Schumacher, Bryan Wayne Pogor, Eric C. Peterson, Lee Thomas VanLanen, Patrick Wesley Clark, Michael Jay Zalta, Scott Stuart Smith, Kirankumar Chhaganlal Patel
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Publication number: 20030046452Abstract: The input/output expansion system (“I/O expansion system”) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.Type: ApplicationFiled: August 31, 2001Publication date: March 6, 2003Inventors: J. Michael Andrewartha, Martha G. Peterson, Farrukh S. Syed, Brent A. Boudreaux, Richard A. Schumacher, Bryan Wayne Pogor, Eric C. Peterson, Lee Thomas VanLanen, Patrick Wesley Clark, Michael Jay Zalta, Scott Stuart Smith, Kirankumar Chhaganlal Patel