Patents by Inventor Bryce D. Horine

Bryce D. Horine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090080832
    Abstract: In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of a quasi-waveguide, and printed circuit board material is laminated to the plated channel using thermoset adhesive. Other embodiments are described and claimed.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 26, 2009
    Inventors: Bryce D. Horine, Gary A. Brist, Stephen H. Hall
  • Patent number: 7480435
    Abstract: In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of an embedded waveguide, and printed circuit board material is laminated to the plated channel. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Bryce D. Horine, Stephen H. Stephen
  • Publication number: 20080172872
    Abstract: In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous material. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Applicant: INTEL CORPORATION
    Inventors: Stephen H. Hall, Bryce D. Horine, Gary A. Brist, Howard Heck
  • Publication number: 20080157903
    Abstract: In some embodiments an interconnect includes a waveguide and a transmission line coupled in parallel with the waveguide. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Stephen H. Hall, Michael T. White, Howard Heck, Bryce D. Horine
  • Patent number: 7249955
    Abstract: In some embodiments an apparatus includes a board, a package coupled to the board, and a flex cable coupled to the package and extending between the board and the package. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 31, 2007
    Assignee: Intel Corporation
    Inventors: Bryce D. Horine, Gary A. Brist
  • Publication number: 20070154157
    Abstract: In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of a quasi-waveguide, and printed circuit board material is laminated to the plated channel using thermoset adhesive. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Bryce D. Horine, Gary A. Brist, Stephen H. Hall
  • Patent number: 6674648
    Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventors: James A. McCall, Bryce D. Horine, Hing Thomas Y. To
  • Publication number: 20030183420
    Abstract: According to the invention, an embodiment of a circuit board includes a substrate having a first layer and a second layer; a surface mount device pad on the first layer of the substrate; and a via, the via being formed wholly or partially through the surface mount device contact and passing through the substrate between the first layer and the second layer.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Terrance J. Dishongh, Bryce D. Horine
  • Patent number: 6587912
    Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Bryce D. Horine, Randy Bonella, Peter D. MacWilliams
  • Publication number: 20030085055
    Abstract: In one embodiment, reducing electromagnetic radiation from sources within a substrate, such as a substrate for supporting an integrated circuit die, where the substrate comprises power layers, ground layers, and ground rings surrounding all or a portion of the power layers, where the ground layers and the ground rings are extended at least to the edges of the substrate so that conductive plates may be in electrical contact with the ground layers and the ground rings so as to define an enclosure to substantially contain electromagnetic radiation from sources within the defined enclosure.
    Type: Application
    Filed: November 5, 2001
    Publication date: May 8, 2003
    Inventors: Harry G. Skinner, Bryce D. Horine
  • Publication number: 20030016516
    Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.
    Type: Application
    Filed: July 23, 2001
    Publication date: January 23, 2003
    Inventors: James A. McCall, Bryce D. Horine, Hing Thomas Y. To
  • Patent number: 6477614
    Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: November 5, 2002
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Bryce D. Horine, Randy Bonella, Peter D. MacWilliams
  • Patent number: 6366466
    Abstract: A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The first signal trace has a relatively thin section and a relatively thick section. The multi-layer printed circuit board also includes a via that couples the first signal trace to the second signal trace. The first signal trace's relatively thin section is located between its relatively thick section and the via.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Bryce D. Horine, James A. McCall
  • Publication number: 20020038405
    Abstract: A memory module includes a first memory bus. A memory repeater hub is coupled to the first memory bus. A second memory bus is coupled in series with the memory repeater hub.
    Type: Application
    Filed: September 30, 1998
    Publication date: March 28, 2002
    Inventors: MICHAEL W. LEDDIGE, BRYCE D. HORINE, RANDY BONELLA, PETER D. MACWILLIAMS
  • Patent number: 6362973
    Abstract: A multi-layer printed circuit board that includes a first layer and a second layer that have first and second signal traces, respectively. The multi-layer printed circuit board includes a via that couples a signal transmitting component to the second signal trace and a throttling member, which is coupled to the first signal trace. The throttling member reduces the speed at which a first signal routed over the first signal trace travels when compared to the speed at which that signal would have traveled had the throttling member been absent.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: March 26, 2002
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Bryce D. Horine
  • Patent number: 6353539
    Abstract: A printed circuit board includes a first component mounted on a first side of the printed circuit board. A second component has an identical pin-out as the first component. The second component is mounted on a second side of the printed circuit board. A first signal line connects a first landpad coupled to a first contact on the first component with a second landpad coupled to a corresponding first contact on the second component. A second signal line connects a third landpad coupled to a second contact on the first component with a fourth land pad coupled to a corresponding second contact on the second component. The first signal line has is equal in length to the second signal line.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: March 5, 2002
    Assignee: Intel Corporation
    Inventors: Bryce D. Horine, Michael W. Leddige
  • Patent number: 6144576
    Abstract: A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: November 7, 2000
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Bryce D. Horine
  • Patent number: 6072699
    Abstract: A printed circuit board (PCB) includes a first 90.degree. signal line. The first 90.degree. signal line connects a first location on a first layer of the PCB to a second location on a second layer of the PCB. The PCB includes a second 90.degree. signal line. The second 90.degree. signal line is adjacent and equal in length to the first 90.degree. signal line. The second 90.degree. signal line connects a third location on the first layer of the PCB to a fourth location on the second layer of the PCB.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: June 6, 2000
    Assignee: Intel Corporation
    Inventor: Bryce D. Horine