Abstract: A device, namely, one of a Field Programmable Gate Array (FPGA) device and an Application Specific Integrated Circuit (ASIC) is described. The FPGA or ASIC is configured to represent one or more pedigree data structures, each structure comprising at least two generations. The device comprises a plurality of logic cells arranged such that one or more of the logic cells model a module of the pedigree data structure, where each module of the pedigree data structure is representative of an individual in a pedigree, input circuitry to receive pedigree data and output circuitry to output processed data; and electrical connections between the logic cells and the input and output circuitry. The arrangement of the logic cells and electrical connections enable parallel processing on a loaded pedigree data structure such that the transmission of pedigree data through at least a subset of the, or each, pedigree data structure occurs in each sampling cycle. A method and data structure are further disclosed.