Patents by Inventor Bu-Ching Lin

Bu-Ching Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110153709
    Abstract: A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 23, 2011
    Inventors: Juinn-Dar HUANG, Jhih-Hong Lu, Bu-Ching Lin, Jing-Yang Jou
  • Patent number: 7577780
    Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 18, 2009
    Assignee: National Chiao Tung University
    Inventors: Juinn-Dar Huang, Bu-Ching Lin, Geeng-Wei Lee, Jing-Yang Jou
  • Publication number: 20080209093
    Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventors: Juinn-Dar Huang, Bu-Ching Lin, Geeng-Wei Lee, Jing-Yang Jou