Patents by Inventor Bu-Il Jung
Bu-Il Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10083764Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.Type: GrantFiled: October 27, 2014Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi-Kyoung Park, Dong-Yang Lee, Sun-Young Lim, Bu-Il Jung, Ju-Yun Jung, Sung-Ho Cho, Hee-Joo Choi, Min-Yeab Choo, Hyuk Han
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Patent number: 9859022Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.Type: GrantFiled: May 27, 2015Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-joong Kim, Soo-hyeong Kim, Sang-hoon Shin, Ju-yun Jung, Ho-young Song, Kyo-min Sohn, Hae-suk Lee, Bu-il Jung, Han-vit Jeong
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Patent number: 9772803Abstract: A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer. Each of the memory blocks includes at least one memory cell row. An address converting circuit along with a block copy circuit performs a block copy operation of copying data of a first memory block, which is a source block among the memory blocks, into a second block, which is a buffer or destination block, and maps a first logical address for accessing the first memory block onto a physical address designating the second block. The first memory block then can serve as a new destination block after the block copy operation of the first memory block is completed.Type: GrantFiled: December 12, 2013Date of Patent: September 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bu-Il Jung, So-Young Kim
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Patent number: 9601218Abstract: A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.Type: GrantFiled: November 3, 2014Date of Patent: March 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Bu-Il Jung, Ju-Yun Jung, Do-Geun Kim, Dong-Yang Lee, Min-Yeab Choo
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Patent number: 9472305Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.Type: GrantFiled: November 6, 2014Date of Patent: October 18, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Yeab Choo, Bu-Il Jung, Do-Geun Kim, Mi-Kyoung Park, Dong-Yang Lee, Sun-Young Lim, Ju-Yun Jung, Hyuk Han
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Patent number: 9275717Abstract: A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.Type: GrantFiled: March 14, 2013Date of Patent: March 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bu-Il Jung, So-Young Kim
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Publication number: 20160048425Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.Type: ApplicationFiled: May 27, 2015Publication date: February 18, 2016Inventors: Hyun-joong Kim, Soo-hyeong Kim, Sang-hoon Shin, Ju-yun Jung, Ho-young Song, Kyo-min Sohn, Hae-suk Lee, Bu-il Jung, Han-vit Jeong
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Patent number: 9257169Abstract: A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.Type: GrantFiled: March 15, 2013Date of Patent: February 9, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bu Il Jung, So Young Kim
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Publication number: 20150199201Abstract: In a method of operating a memory system including a memory device, a memory controller and a host according to example embodiments, a hardware is initialized based on a fail information and a boot code stored in a nonvolatile memory of a volatile memory and the nonvolatile memory included in the memory device. A host processes data in an internal memory included in the memory controller and a safe region included in the memory device based on the fail information. Using the fail information, the method of operating the memory system according to example embodiments increases the performance of the whole system including the memory system.Type: ApplicationFiled: October 27, 2014Publication date: July 16, 2015Inventors: SUN-YOUNG LIM, MIN-YEAB CHOO, MI-KYOUNG PARK, DONG-YANG LEE, BU-IL JUNG, JU-YUN JUNG, HYUK HAN
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Publication number: 20150199230Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.Type: ApplicationFiled: October 27, 2014Publication date: July 16, 2015Inventors: MI-KYOUNG PARK, Dong-Yang Lee, Sun-Young Lim, Bu-Il Jung, Ju-Yun Jung, Sung-Ho Cho, Hee-Joo Choi, Min-Yeab Choo, Hyuk Han
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Publication number: 20150169333Abstract: A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.Type: ApplicationFiled: November 3, 2014Publication date: June 18, 2015Inventors: Bu-Il JUNG, Ju-Yun JUNG, Do-Geun KIM, Dong-Yang LEE, Min-Yeab CHOO
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Publication number: 20150131393Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: Min-Yeab CHOO, Bu-Il JUNG, Do-Geun KIM, Mi-Kyoung PARK, Dong-Yang LEE, Sun-Young LIM, Ju-Yun JUNG, Hyuk HAN
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Publication number: 20150128000Abstract: In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system.Type: ApplicationFiled: November 3, 2014Publication date: May 7, 2015Inventors: Ju-Yun JUNG, Min-Yeab CHOO, Do-Geun KIM, Mi-Kyoung PARK, Dong-Yang LEE, Sun-Young LIM, Bu-Il JUNG, Hyuk HAN
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Patent number: 8874996Abstract: A memory device comprises a normal storage area comprising first and second subsets configured to store first and second normal data, respectively, an error code storage area configured to store first and second error codes corresponding to the first and second normal data, an error detector configured to receive the first and second normal data and the first and second error codes, and further configured to detect the presence or absence of one or more errors in the first and second normal data or the first and second error codes, and a refresh controller configured to set respective refresh cycle times of the first and second subsets to different values according to the presence or absence of one or more errors in the first and second normal data or error codes.Type: GrantFiled: August 29, 2012Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Bu-Il Jung
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Publication number: 20140173234Abstract: A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer. Each of the memory blocks includes at least one memory cell row. An address converting circuit along with a block copy circuit performs a block copy operation of copying data of a first memory block, which is a source block among the memory blocks, into a second block, which is a buffer or destination block, and maps a first logical address for accessing the first memory block onto a physical address designating the second block. The first memory block then can serve as a new destination block after the block copy operation of the first memory block is completed.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: BU-IL JUNG, So-Young KIM
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Publication number: 20140029367Abstract: A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.Type: ApplicationFiled: March 14, 2013Publication date: January 30, 2014Inventors: Bu-Il JUNG, So-Young KIM
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Publication number: 20130304982Abstract: A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.Type: ApplicationFiled: March 15, 2013Publication date: November 14, 2013Inventors: Bu Il JUNG, So Young KIM
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Publication number: 20130111296Abstract: A memory device comprises a normal storage area comprising first and second subsets configured to store first and second normal data, respectively, an error code storage area configured to store first and second error codes corresponding to the first and second normal data, an error detector configured to receive the first and second normal data and the first and second error codes, and further configured to detect the presence or absence of one or more errors in the first and second normal data or the first and second error codes, and a refresh controller configured to set respective refresh cycle times of the first and second subsets to different values according to the presence or absence of one or more errors in the first and second normal data or error codes.Type: ApplicationFiled: August 29, 2012Publication date: May 2, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: BU-IL JUNG
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Patent number: 7586360Abstract: The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.Type: GrantFiled: February 21, 2007Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Bu-Il Jung
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Patent number: 7492654Abstract: A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.Type: GrantFiled: June 12, 2006Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-Gyoo Won, Bu-Il Jung