Abstract: A semiconductor memory device includes a plurality of output buffer units connected to a plurality of terminals. Each of the output buffer units includes a first high speed data output (HSDO) buffer adapted to buffer even-numbered data of a corresponding data row among a plurality of data rows and to output the even-numbered data to a corresponding terminal among the plurality of terminals, a second HSDO buffer adapted to buffer odd-numbered data of the corresponding data row and to output the odd-numbered data to the corresponding terminal, and a buffer selector adapted to select and activate the first HSDO buffer and/or the second HSDO buffer in response to a corresponding control signal out of at least one control signal during a HSDO test.