Patents by Inventor Bu-Qing Ping

Bu-Qing Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transaction layer circuit of PCIe and operation method thereof
    Patent number: 11726944
    Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: August 15, 2023
    Assignees: Faraday Technology Corporation, Faraday Technology Corp.
    Inventor: Bu-Qing Ping
  • TRANSACTION LAYER CIRCUIT OF PCIE AND OPERATION METHOD THEREOF
    Publication number: 20230029065
    Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.
    Type: Application
    Filed: December 6, 2021
    Publication date: January 26, 2023
    Applicants: Faraday Technology Corporation, Faraday Technology Corp.
    Inventor: Bu-Qing Ping