Patents by Inventor Bu-Won Kim

Bu-Won Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210580
    Abstract: A semiconductor device includes a package substrate including substrate pads and a first, second, and third semiconductor chips sequentially stacked on the package substrate. The first semiconductor chip includes first signal pads and first dummy pads in a line, the second semiconductor chip includes second signal pads and third signal pads disposed in a line, the third semiconductor chip includes fourth signal pads disposed in a line. The first signal pads correspond to the second signal pads, the first dummy pads correspond to the third signal pads, the third signal pads correspond to the fourth signal pads, on a one-to-one basis.
    Type: Application
    Filed: October 16, 2024
    Publication date: June 26, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hee Woo AN, Bu-Won KIM
  • Publication number: 20250070088
    Abstract: A semiconductor package includes: a substrate including a plurality of connection pads; a first semiconductor chip on the substrate and including a plurality of first data pads on an upper surface thereof; a second semiconductor chip on the first semiconductor chip and including a plurality of second data pads on an upper surface thereof; a third semiconductor chip on the second semiconductor chip and including a plurality of third data pads on an upper surface thereof; and a plurality of connection members for connecting some of the plurality of connection pads and some of the plurality of first data pads, connecting the plurality of connection pads and the plurality of second data pads, and connecting some of the plurality of second data pads and some of the plurality of third data pads.
    Type: Application
    Filed: May 10, 2024
    Publication date: February 27, 2025
    Inventors: JINHEE HONG, BU-WON KIM
  • Patent number: 10714416
    Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bu-won Kim, Dae-ho Lee, Hee-jin Lee
  • Publication number: 20190221512
    Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Bu-Won Kim, Dae-ho Lee, Hee-jin Lee
  • Patent number: 10304766
    Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bu-won Kim, Dae-ho Lee, Hee-jin Lee
  • Publication number: 20190051592
    Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.
    Type: Application
    Filed: January 26, 2018
    Publication date: February 14, 2019
    Inventors: BU-WON KIM, Dae-ho Lee, Hee-jin Lee
  • Publication number: 20120315726
    Abstract: Provided are methods of manufacturing a semiconductor chip package. The method includes forming a plurality of semiconductor chips, each of which includes a semiconductor substrate having a front and back surfaces facing each other, a chip pad provided on the front surface of the semiconductor substrate, and an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate, stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other, and reflowing the interconnection patterns of the semiconductor chips to connect the stacked semiconductor chips with each other.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 13, 2012
    Inventors: HAK-KYOON BYUN, Bu-Won Kim, Raehyung Do, JongBo Shim, Woodong Lee