Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: Methods and systems for a reversible top/bottom MEMS package may comprise a base substrate comprising metal traces, an opening through the base substrate, a die coupled to a first surface of the substrate and positioned over the opening, a frame member coupled to the first surface of the substrate wherein the die is positioned interior of the frame member, a cover substrate coupled to the frame member, and conductive plating on the frame member that electrically couples the base substrate to the cover substrate, wherein the conductive plating is exposed. The conductive plating may couple a ground plane in the base substrate to a ground plane in the cover substrate. The conductive plating may be exposed at an outer surface of the frame member and/or at an inner perimeter of the frame member. Conductive vias within the frame member may be coupled to the metal traces in the base substrate.

Abstract: Methods and systems for a reversible top/bottom MEMS package may comprise a base substrate comprising metal traces, an opening through the base substrate, a die coupled to a first surface of the substrate and positioned over the opening, a frame member coupled to the first surface of the substrate wherein the die is positioned interior of the frame member, a cover substrate coupled to the frame member, and conductive plating on the frame member that electrically couples the base substrate to the cover substrate, wherein the conductive plating is exposed. The conductive plating may couple a ground plane in the base substrate to a ground plane in the cover substrate. The conductive plating may be exposed at an outer surface of the frame member and/or at an inner perimeter of the frame member. Conductive vias within the frame member may be coupled to the metal traces in the base substrate.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. A cover substrate having a plurality of metal traces and a plurality of cover vias is provided. A first die is attached to the first surface of the substrate and positioned over the opening. Side members are coupled to ground planes on the base substrate and cover substrate to form an RF shield around the first die. At least one wirebond having a first end attached to the first die and a second end attached to a metal trace of the base substrate is provided. The at least one wirebond forms a loop wherein a top section of the loop contacts a metal trace of the cover substrate.