Patents by Inventor Buderya Acharya

Buderya Acharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070073977
    Abstract: In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventors: Robert Safranek, Robert Greiner, David Hill, Buderya Acharya, Zohar Bogin, Derek Bachand, Robert Beers
  • Publication number: 20070005934
    Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Applicant: Intel Corporation (a Delaware corporation)
    Inventors: Hemant Rotithor, Abhishek Singhal, Randy Osborne, Zohar Bogin, Raul Gutierrez, Buderya Acharya, Surya Kareenahalli
  • Publication number: 20050273400
    Abstract: Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 8, 2005
    Inventors: Robert Blankenship, Robert Greiner, Herbert Hum, Kenneth Creta, Buderya Acharya