Abstract: An image processing apparatus is provided that is capable of performing combining processing of image from image processing sections without the intermediation of a frame buffer, and can reduce the delay between image input and display and improve real-time capability. An image processing main chip 110 of a three-input image processing system 100 reads image data stored in frame buffers of storage apparatuses 117 through 119 in accordance with the line frequency of a display section 114, collects, in line units, image data processed by image processing subchips 111 and 112, performs combining processing in line units of the collected image data and image data it has processed itself, and outputs the combined data to display section 114, and image processing subchips 111 and 112 transfer processed image data to image processing main chip 110 in line units.