Patents by Inventor Budy Darmono Notohardjono

Budy Darmono Notohardjono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6255832
    Abstract: A test probe head has a plurality of electrically conducting wire members held in place in a frame by movable plates. The wire members are threaded through apertures in the plates and the plates are moved relative to each other to bend the wires to thereby hold the wires in position in the frame. The wires are used to make physical contact with both a support substrate for the test probe head and an integrated circuit under test. The physical contact of the wires with both the substrate and the integrated circuit provides electrical connections between the pads in the support substrate and those on the integrated circuit to perform the testing of the integrated circuit. With this arrangement, there is no bonding of the wires to the pads of the support substrate. The elimination of the bonding to the pads of the support substrate eliminates a major cause of probe head failures.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: July 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: Budy Darmono Notohardjono, Roger Ray Schmidt, Prabjit Singh
  • Patent number: 5744975
    Abstract: A method for testing electronic assemblies having an electronic component affixed via solder or other such connections to a printed circuit board. The method includes combining, in order, three sequential stress test steps, into a single stress test for screening defects in the electronic assemblies. In particular, the test combines a thermal cycling stress test followed by a electrical burn-in stress test coupled with functional monitoring of the assembly, followed by a random vibration stress test coupled with functional monitoring of the assembly, each test is imposed with defined parameters upon the electronic assembly. The combination, order, and parameters of the sequential stress test steps provide a single test for electrical assemblies which substantially screens all such assemblies having systematic or random defects while imparting minimal reduction in useful life to the defect-free assemblies by virtue of the testing, thereby resulting in a high reliability product.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: April 28, 1998
    Assignee: International Business Machines Corporation
    Inventors: Budy Darmono Notohardjono, Vincent Cozzolino