Patents by Inventor Buford M. Guy

Buford M. Guy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10282296
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, David Papworth, James D. Allen
  • Patent number: 10228941
    Abstract: A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Bret L. Toll, Ronak Singhal, Buford M. Guy, Mishali Naik
  • Publication number: 20190012266
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Publication number: 20180293074
    Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.
    Type: Application
    Filed: June 1, 2018
    Publication date: October 11, 2018
    Inventors: Bret L. TOLL, Buford M. GUY, Ronak SINGHAL, Mishali NAIK
  • Publication number: 20180165199
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 9990202
    Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Bret L. Toll, Ronak Singhal, Buford M. Guy, Mishali Naik
  • Patent number: 9934032
    Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Seyed Yahya Sotoudeh, Buford M. Guy
  • Publication number: 20170109164
    Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 20, 2017
    Applicant: lntel Corporation
    Inventors: Edward T. Grochowski, Seyed Yahya Sotoudeh, Buford M. Guy
  • Patent number: 9477467
    Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
    Type: Grant
    Filed: March 30, 2013
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Seyed Yahya Sotoudeh, Buford M. Guy
  • Publication number: 20150186140
    Abstract: Embodiments of an invention for opcode trapping are disclosed. In one embodiment, a processor includes an instruction unit to receive an instruction, the instruction unit having a match storage location in which to store a match value and a comparator. The comparator is to compare the match value to a portion of the instruction. Control of the processor is to be transferred to a trap handler if the comparator indicates that the match value matches the portion of the instruction.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: Bret L. Toll, Buford M. Guy, Ronak Singhal, Glenn J. Hinton, Mishali Naik
  • Publication number: 20150006858
    Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: BRET L. TOLL, Buford M. Guy, Ronak Singhal, Mishali Nail
  • Publication number: 20150006865
    Abstract: A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Bret L. TOLL, Ronak SINGHAL, Buford M. GUY, Mishali NAIK
  • Publication number: 20140297994
    Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
    Type: Application
    Filed: March 30, 2013
    Publication date: October 2, 2014
    Inventors: Edward T. Grochowski, Seyed Yahya Sotoudeh, Buford M. Guy
  • Publication number: 20020170038
    Abstract: The present invention pertains to multi-computer communication systems and the testing of computer systems in such systems. To reduce expenditures in time and money, a computer system can be performance tested for a multi-computer communications environment without the necessity of creating a communications network. Instead the computer system under test executes server and client code and transmits data packets according to one more standard network communications protocols (e.g., SSL). Thread execution time is tracked along with the number of transactions completed between the execution of server code and the execution of client code. With this data, the performance of the computer system acting solely as a server or as a client can be determined.
    Type: Application
    Filed: May 8, 2001
    Publication date: November 14, 2002
    Inventors: Bernard Yeh, Buford M. Guy, Mohammed B. Zaidi, Saikat ?quot;Roy?quot; Saharoy