Patents by Inventor Bulent I. Dervisoglu

Bulent I. Dervisoglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8239716
    Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: August 7, 2012
    Assignee: Intellectual Ventures I LLC
    Inventors: Bulent I. Dervisoglu, Laurence H. Cooke, Vacit Arat
  • Patent number: 7890899
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 15, 2011
    Assignee: Intellectual Ventures I LLC
    Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
  • Patent number: 7752515
    Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: July 6, 2010
    Inventors: Bulent I. Dervisoglu, Laurence H. Cooke
  • Publication number: 20080163020
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 3, 2008
    Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
  • Patent number: 7353470
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: April 1, 2008
    Assignee: On-Chip Technologies, Inc.
    Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
  • Patent number: 6594802
    Abstract: An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e.g., it may be programmed into a programmable logic device by the test resource apparatus.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: July 15, 2003
    Assignee: Intellitech Corporation
    Inventors: Michael Ricchetti, Christopher J. Clark, Bulent I. Dervisoglu
  • Patent number: 5257223
    Abstract: A scannable flip-flop circuit allows data at its data input or its scan input to be stored in the flip-flop at its data output or shifted out of the flip-flop at its scan output. The flip-flop provides control circuitry for selecting the source of the input data and scan data. Data stored at the flip-flop data output may also be shifted out at the scan output. During scan operations, additional control circuitry allows data stored at the data outputs to be preserved.
    Type: Grant
    Filed: November 13, 1991
    Date of Patent: October 26, 1993
    Assignee: Hewlett-Packard Company
    Inventor: Bulent I. Dervisoglu
  • Patent number: 5068881
    Abstract: A scan-register having first and second data input ports (SYS.sub.-- DATA, SCAN.sub.-- IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS.sub.-- CLK, M.sub.-- LOAD, CLK.sub.-- B, CLK.sub.-- A).
    Type: Grant
    Filed: August 10, 1990
    Date of Patent: November 26, 1991
    Assignee: Hewlett-Packard Company
    Inventors: Bulent I. Dervisoglu, Gayvin E. Stong