Abstract: Disclosed is a method for fabricating a gate of semiconductor device. The disclosed comprises the steps of: sequentially forming a gate oxide layer, a gate material layer and a mask oxide layer on a semiconductor substrate; coating photopolymer having compound accelerator including polar functional group which absorbs HF vapor and ionize at a predetermined high temperature on the mask oxide layer; exposing the photopolymer and cross-linking the portion of exposed photopolymer; performing DFVP process by passing over HF vapor on the resultant substrate at a predetermined high temperature, thereby developing the portion of exposed photopolymer and etching the portion of mask oxide layer exposed by development of photopolymer simultaneously; removing the residual photopolymer; and etching the gate material layer and the gate oxide layer using the etched mask oxide layer.

Abstract: Disclosed is a method for fabricating a gate of semiconductor device. The disclosed comprises the steps of: sequentially forming a gate oxide layer, a gate material layer and a mask oxide layer on a semiconductor substrate; coating photopolymer having compound accelerator including polar functional group which absorbs HF vapor and ionize at a predetermined high temperature on the mask oxide layer; exposing the photopolymer and cross-linking the portion of exposed photopolymer; performing DFVP process by passing over HF vapor on the resultant substrate at a predetermined high temperature, thereby developing the portion of exposed photopolymer and etching the portion of mask oxide layer exposed by development of photopolymer simultaneously; removing the residual photopolymer; and etching the gate material layer and the gate oxide layer using the etched mask oxide layer.

Abstract: A method for forming fine patterns and a using the method for forming gate electrodes of a semiconductor device are provided. The gate electrodes are formed by: forming a gate insulation layer over a semiconductor wafer; forming a conductive layer for the gate electrodes over the gate insulation layer; forming a low-dielectric layer over the conductive layer for the gate electrodes; forming a photoresist pattern whose width is equal to the exposure limit on the low-dielectric layer; patterning the low-dielectric layer using the photoresist pattern as a mask; removing the photoresist pattem; shrinking the low-dielectric pattern; and patterning the conductive layer for gate electrodes and the gate insulation layer using the shrunken low-dielectric pattern as a mask, thereby forming the gate electrodes.

Abstract: The present invention discloses a method for forming a gate having a stacked structure, including a lower polysilicon layer and an upper Co-silicide layer, by etching the stacked layers using a hard mask film as an etching mask. The etching process is performed by maintaining a temperature of a wafer chuck in an etching chamber where a substrate is positioned, namely an electrode temperature over 70° C., preferably between 70 and 300° C., and by using Cl2 base gas. In addition, at least one gas selected from the group consisting of Ar, HBr, O2 and He—O2 may be mixed with the Cl2 gas.