Patents by Inventor Bum-Ki Baek
Bum-Ki Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110156046Abstract: A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.Type: ApplicationFiled: December 24, 2010Publication date: June 30, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon-Ju KIM, Sung-Jae MOON, Yun-Jung CHO, Bum-Ki BAEK, Kwang-Hoon LEE, Byoung-Sun NA, Sung-Hoon YANG, Yoon-Jang KIM, Eun CHO
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Patent number: 7944535Abstract: A liquid crystal display includes opening patterns in the electrodes or protrusions on the electrodes. The opening patterns or the protrusions have a pattern which controls the direction of the liquid crystal molecules. Thus the quality of the LCD can be improved.Type: GrantFiled: July 31, 2008Date of Patent: May 17, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Joon Kim, Bum-Ki Baek, Jeong-Young Lee, Jae-Hong Jeon
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Patent number: 7888677Abstract: A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern.Type: GrantFiled: May 18, 2009Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Yong Park, Bum-Ki Baek
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Patent number: 7742118Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: March 23, 2007Date of Patent: June 22, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20090294771Abstract: A substrate for a display panel includes a base substrate, a plurality of signal lines, a plurality of signal pads corresponding to first end portions of the signal lines, a shorting bar corresponding to second end portions of the signal lines, a plurality of bridge lines on the base substrate disposed between the signal line and the shorting bar which electrically connects the signal line and the shorting bar. A color filter array panel opposite a TFT LCD panel substrate includes a medium dam layer which fully overlaps the bridge lines of the TFT LCD panel substrate. A data TFT for inspection having a source electrode coupled to the signal line, a drain electrode coupled to any one of the shorting bars, and a gate electrode coupled to a data TFT driving signal line ensures the normal operation of the display panel after the array test.Type: ApplicationFiled: July 31, 2008Publication date: December 3, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Beom-Jun KIM, Jong-Hwan LEE, Bum-Ki BAEK, Sung-Man KIM, Hye-Rhee HAN, Jong-Hyuk LEE, Yu-Jun KIM
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Publication number: 20090283769Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.Type: ApplicationFiled: May 18, 2009Publication date: November 19, 2009Inventors: Woon-Yong PARK, Bum-Ki Baek
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Patent number: 7566906Abstract: A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.Type: GrantFiled: December 17, 2007Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, San-Jin Jeon
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Patent number: 7541225Abstract: A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.Type: GrantFiled: January 13, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Hyuk-Jin Kim
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Patent number: 7537977Abstract: A thin film transistor (TFT) array panel that includes a substrate, a gate wire formed on the substrate, a gate insulating layer pattern formed on the gate wire, a semiconductor layer pattern formed on the gate insulating layer pattern, an ohmic contact layer pattern formed on the semiconductor layer pattern, a data wire formed on the ohmic contact layer pattern, a passivation layer pattern formed on the data wire, and a pixel electrode is presented. The data wire includes a data pad. The ohmic contact layer pattern includes a portion disposed under the data pad that is simultaneously etched as the data pad, and a contact hole in the passivation layer is etched simultaneously as a contact hole in the gate insulating layer.Type: GrantFiled: March 9, 2007Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Yong Park, Bum-Ki Baek
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Patent number: 7507994Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.Type: GrantFiled: January 22, 2007Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Ki Baek, Mun-Pyo Hong, Jang-Soo Kim, Sung-Wook Hao, Jong-Soo Yoon, Doug-Gyu Kim
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Patent number: 7459323Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconType: GrantFiled: August 30, 2006Date of Patent: December 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Sang-Jin Jeon, Jung-Joon Park, Jeong-Young Lee, Bum-Ki Baek, Se-Hwan Yu, Sang-Ki Kwak, Han-Ju Lee, Kwon-Young Choi
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Publication number: 20080284961Abstract: A liquid crystal display includes opening patterns in the electrodes or protrusions on the electrodes. The opening patterns or the protrusions have a pattern which controls the direction of the liquid crystal molecules. Thus the quality of the LCD can be improved.Type: ApplicationFiled: July 31, 2008Publication date: November 20, 2008Inventors: Hee-Joon Kim, Bum-Ki Baek, Jeong-Young Lee, Jae-Hong Jeon
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Patent number: 7440040Abstract: A liquid crystal display (LCD) includes a gate line, a data line, and a pixel electrode including first and second sub-pixel electrodes to which different voltages are applied. A thin film transistor is coupled with the gate line and the data line to apply a voltage to the pixel electrode, and a storage electrode partially overlaps with the first and second sub-pixel electrodes. The first sub-pixel electrode is arranged on all but one side of the second sub-pixel electrode, portions of a first side of the storage electrode overlap with the boundaries of the first and second sub-pixel electrodes, portions of a second side of the storage electrode protrude and partially overlap with the second sub-pixel electrode, and the storage electrode comprises a storage electrode extension, which protrudes from the second side of the storage electrode across the first sub-pixel electrode and overlaps with the second sub-pixel electrode.Type: GrantFiled: July 27, 2006Date of Patent: October 21, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Ki Kwak, Jung-Joon Park, Bum-Ki Baek, Kyung-Phil Lee
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Publication number: 20080252806Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: June 18, 2008Publication date: October 16, 2008Inventors: Jun-Hyung SOUK, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Patent number: 7420639Abstract: A liquid crystal display includes opening patterns in the electrodes or protrusions on the electrodes. The opening patterns or the protrusions have a pattern which controls the direction of the liquid crystal molecules. Thus the quality of the LCD can be improved.Type: GrantFiled: January 27, 2005Date of Patent: September 2, 2008Assignee: Samsung Electronics Co, Ltd.Inventors: Hee-Joon Kim, Bum-Ki Baek, Jeong-Young Lee, Jae-Hong Jeon
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Patent number: 7403240Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: April 27, 2007Date of Patent: July 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20080093600Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: ApplicationFiled: December 17, 2007Publication date: April 24, 2008Inventors: Min-Wook PARK, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, Sang-Jin Jeon
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Patent number: 7320906Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: GrantFiled: August 19, 2004Date of Patent: January 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, Sang-Jin Jeon
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Publication number: 20070222727Abstract: A display device includes a signal line formed on a substrate, a repair line formed on the substrate crossing and insulated from the signal line, and a first redundancy conductive pattern formed on a first region of the substrate where the signal line crosses the repair line, wherein the first redundancy conductive pattern is insulated from the signal line and the repair line.Type: ApplicationFiled: February 27, 2007Publication date: September 27, 2007Inventors: Bum Ki Baek, Dong Il Son
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Patent number: 7265799Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: January 16, 2004Date of Patent: September 4, 2007Assignee: Samsung Electronics Co., LtdInventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek