Patents by Inventor BUM KYU KANG
BUM KYU KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961720Abstract: Disclosed herein is a multi-channel device for detecting plasma at an ultra-fast speed, including: a first antenna module connected to a first output terminal in contact with a substrate on a chuck of a process chamber and extending to ground, and receiving a first leakage current leaking through the substrate to increase reception sensitivity of the leakage current; a first current detection module detecting the first leakage current; a current measurement module receiving the first leakage current output from the first current detection module, and extracting the received first leakage current for each predetermined period to generate a first leakage current measurement information; and a control module comparing the first leakage current measurement information with a reference value to generate first arcing occurrence information.Type: GrantFiled: October 12, 2021Date of Patent: April 16, 2024Assignee: T.O.S Co., Ltd.Inventors: Yong Kyu Kim, Bum Ho Choi, Yong Sik Kim, Kwang Ki Kang, Hong Jong Jung, Seok Ho Lee, Seung Soo Lee
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Publication number: 20240055486Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Ji Young KIM, Dong-Sik LEE, Joon-Sung LIM, Bum Kyu KANG, Ho Jun SEONG
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Publication number: 20230413545Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: ApplicationFiled: August 4, 2023Publication date: December 21, 2023Inventors: Sung Min Hwang, Joon Sung Lim, Bum Kyu Kang, Jae Ho Ahn
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Patent number: 11758719Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: GrantFiled: August 2, 2021Date of Patent: September 12, 2023Inventors: Sung Min Hwang, Joon Sung Lim, Bum Kyu Kang, Jae Ho Ahn
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Publication number: 20220336586Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.Type: ApplicationFiled: October 18, 2021Publication date: October 20, 2022Inventors: Ji Young KIM, Dong-Sik LEE, Joon-Sung LIM, Bum Kyu KANG, Ho Jun SEONG
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Publication number: 20220246643Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Inventors: Jae Ho AHN, Sung-Min HWANG, Joon-Sung LIM, Bum Kyu KANG, Sang Don LEE
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Patent number: 11315947Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.Type: GrantFiled: June 2, 2020Date of Patent: April 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ho Ahn, Sung-Min Hwang, Joon-Sung Lim, Bum Kyu Kang, Sang Don Lee
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Publication number: 20210358933Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Inventors: SUNG MIN HWANG, JOON SUNG LIM, BUM KYU KANG, JAE HO AHN
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Patent number: 11088157Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: GrantFiled: August 17, 2019Date of Patent: August 10, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Min Hwang, Joon Sung Lim, Bum Kyu Kang, Jae Ho Ahn
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Publication number: 20210111187Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.Type: ApplicationFiled: June 2, 2020Publication date: April 15, 2021Inventors: Jae Ho AHN, Sung-Min HWANG, Joon-Sung LIM, Bum Kyu KANG, Sang Don LEE
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Publication number: 20200135749Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.Type: ApplicationFiled: August 17, 2019Publication date: April 30, 2020Inventors: SUNG MIN HWANG, JOON SUNG LIM, BUM KYU KANG, JAE HO AHN