Patents by Inventor Bum-Seok Kim

Bum-Seok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107101
    Abstract: Provided is an input device which allows a user to select desired contents more quickly and intuitively in selection of contents. The input device includes: a navigation key manipulated to select one direction among a plurality of directions; a dial unit including a rotating dial wheel; and a control unit which controls movement on a user interface screen of a target device based on one or more direction inputs corresponding to the navigation key and a rotation operation input of the dial wheel, wherein the navigation key and the dial wheel are coupled with each other in a stacked structure.
    Type: Application
    Filed: November 3, 2021
    Publication date: March 28, 2024
    Inventor: Bum Seok KIM
  • Publication number: 20230421834
    Abstract: Provided is an input device which allows a user to select desired contents more quickly and intuitively in selection of contents. The input device includes: a navigation key manipulated to select one direction among a plurality of directions; a touch unit which is manipulated by a user to input rotation while the user touches the touch unit with a portion of the body; and a control unit which controls movement on a user interface screen of a target device based on one or more direction inputs corresponding to the navigation key and a rotation input on the touch unit, wherein the navigation key and the touch unit are coupled with each other in a stacked structure.
    Type: Application
    Filed: November 3, 2021
    Publication date: December 28, 2023
    Inventor: Bum Seok KIM
  • Publication number: 20230197368
    Abstract: A remote control with a waterproof function, according to an embodiment of the present invention, includes a case including an upper case having a plurality of button holes and a lower case assembled to the upper case at a lower portion of the upper case, a printed circuit board PCB embedded between the upper case and the lower case, and a rubber keypad, which is embedded between the upper case and the lower case so as to mounted to surround the side portions of the PCB and has a plurality of buttons that pass through the plurality of button holes and barrier parts that come into close contact with the inner surface of the upper case and the inner surface of the lower case, where the upper case and the lower case come into contact with each other.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: Bum Seok KIM, Jung Il AN
  • Publication number: 20230199985
    Abstract: A remote control with a waterproof function includes a case including an upper case having button holes and a lower case assembled to the upper case at a lower portion of the upper case, a printed circuit board PCB embedded between the both cases, and a rubber keypad embedded in the case so as to be positioned between the upper case and the PCB and having buttons passing through the button holes. Barriers protruding upward or downward along the edges of the rubber keypad are provided, and when the both cases are coupled with the rubber keypad interposed therebetween, the side portions of the lower case and the lower ends of the barriers are in close contact with each other and the inner surface of the upper case and the upper ends of the barriers are in close contact with each other, thereby providing waterproof function.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Inventors: Bum Seok KIM, Jung Il AN
  • Patent number: 10991786
    Abstract: A signal control unit for an organic light emitting diode (OLED) display device includes a substrate structure including a plurality of active elements for the pixels, first metal electrodes disposed on the substrate structure, and configured to be electrically connected to a portion of each of the active elements, second metal electrodes disposed over and adjacent the first metal electrodes, configured to electrically connected to corresponding ones of the first metal electrodes, respectively, by via contacts extending vertically to electrically connect the first metal electrodes to the second metal electrodes, and interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure having a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked in order.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 27, 2021
    Assignee: DB HITEK CO., LTD.
    Inventors: Jin Hyo Jung, Jung Hyun Lee, Dae Il Kim, Bum Seok Kim, Seung Ha Lee, Sang Yong Lee, Dong Hoon Park
  • Patent number: 10811311
    Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 20, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Dong Hoon Park, Jung Hyun Lee, Dae Il Kim, Bum Seok Kim, Jin Hyo Jung, Seung Ha Lee, Sang Yong Lee
  • Publication number: 20200029445
    Abstract: Disclosed is a cavity forming method for a printed circuit board. The method includes: stacking a plurality of substrates to form a stacked structure, each substrate including a prepreg and a copper clad circuit formed on a surface of the prepreg; attaching a release film to an outer surface of the stacked structure; demarcating a cavity region by forming a cutting line in the release film and the underlying prepreg; and removing the released film and the underlying prepreg inside the demarcated cavity region, thereby forming a cavity. The method is advantageous in terms of easy processing, mass production, and low manufacturing cost for printed circuit boards. Further, a cavity having an exactly same size as an actually required size can be designed for a printed circuit board, and it is possible to prevent an adhesive component from seeping out into a cavity from prepregs during formation of the cavity.
    Type: Application
    Filed: December 18, 2018
    Publication date: January 23, 2020
    Inventors: Bum-Seok Kim, Dae-Soo Park
  • Publication number: 20190221476
    Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 18, 2019
    Inventors: Dong Hoon Park, Jung Hyun Lee, Dae Il Kim, Bum Seok Kim, Jin Hyo Jung, Seung Ha Lee, Sang Yong Lee
  • Publication number: 20190088732
    Abstract: A signal control unit for an organic light emitting diode (OLED) display device includes a substrate structure including a plurality of active elements for the pixels, first metal electrodes disposed on the substrate structure, and configured to be electrically connected to a portion of each of the active elements, second metal electrodes disposed over and adjacent the first metal electrodes, configured to electrically connected to corresponding ones of the first metal electrodes, respectively, by via contacts extending vertically to electrically connect the first metal electrodes to the second metal electrodes, and interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure having a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked in order.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 21, 2019
    Inventors: Jin Hyo JUNG, Jung Hyun LEE, Dae Il KIM, Bum Seok KIM, Seung Ha LEE, Sang Yong LEE, Dong Hoon PARK
  • Publication number: 20190088780
    Abstract: A DEMOS transistor includes a semiconductor substrate defining a field region and an active region, a gate pattern disposed on the semiconductor substrate, the gate pattern being positioned over both the active region and the field region, drift regions disposed in the active region and positioned adjacent to both sides of the gate pattern, high concentration ion regions disposed in the drift regions, and being spaced apart from the gate pattern, and a silicide blocking layer having a exposure hole exposing one of an upper surface of the gate pattern and the high concentration ion regions, the silicide blocking layer having a ring shape to at least partially surround one of the upper surface of the gate pattern and the high concentration ion regions.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 21, 2019
    Inventors: Kee Joon CHOI, Bon Sug KOO, Bum Seok KIM, Mi Hye JUN, Hae Taek KIM, Duk Joo WOO
  • Patent number: 10217857
    Abstract: A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventors: Young Seok Kim, Bum Seok Kim
  • Patent number: 10008594
    Abstract: A high voltage semiconductor device includes a gate electrode structure disposed on a substrate, a source region disposed in the substrate to be adjacent to one side of the gate electrode structure, a first drift region disposed in the substrate to be adjacent to another side of the gate electrode structure, a drain region electrically connected with the first drift region, and a device isolation region disposed on one side of the drain region. Particularly, the first drift region is spaced apart from the device isolation region.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 26, 2018
    Assignee: DB HITEK CO., LTD.
    Inventors: Kee Joon Choi, Bum Seok Kim, Bon Sug Koo, Mi Hye Jun, Hae Taek Kim, Duk Joo Woo
  • Patent number: 9941364
    Abstract: In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 10, 2018
    Assignee: DB HITEK CO., LTD.
    Inventors: Jin Hyo Jung, Jung Hyun Lee, Bum Seok Kim, Seung Ha Lee, Chang Hee Kim
  • Publication number: 20180012990
    Abstract: A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 11, 2018
    Inventors: Young Seok KIM, Bum Seok KIM
  • Publication number: 20170278922
    Abstract: A high voltage semiconductor device includes a gate electrode structure disposed on a substrate, a source region disposed in the substrate to be adjacent to one side of the gate electrode structure, a first drift region disposed in the substrate to be adjacent to another side of the gate electrode structure, a drain region electrically connected with the first drift region, and a device isolation region disposed on one side of the drain region. Particularly, the first drift region is spaced apart from the device isolation region.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 28, 2017
    Inventors: Kee Joon Choi, Bum Seok Kim, Bon Sug Koo, Mi Hye Jun, Hae Taek Kim, Duk Joo Woo
  • Publication number: 20150162346
    Abstract: Disclosed is a semiconductor package. The semiconductor package includes a substrate formed with transistors, power metal lines formed on the substrate, data metal lines formed on the substrate to transmit and receive data to and from the transistors, and an insulating layer formed on the substrate, the power metal lines, and the data metal lines. Herein, the insulating layer has openings partially exposing the power metal lines.
    Type: Application
    Filed: June 10, 2014
    Publication date: June 11, 2015
    Inventors: Kee Joon Choi, Bum Seok Kim, Moon Young Lee, Sun Young Lee
  • Publication number: 20080293205
    Abstract: A method of forming a metal silicide layer includes sequentially forming a metal layer and a first capping layer on a substrate, performing a first heat treatment on the substrate to cause the substrate to react to the metal layer, removing the first, capping layer and an unreacted metal layer, forming a second capping layer on the substrate, and performing a second heat treatment on the substrate to form a metal silicide layer on the substrate.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 27, 2008
    Inventors: Oh-Kyum KWON, Bum-Seok KIM, Geun-Sook PARK, Joon-Suk OH, Hye-Young PARK, Min-Jun CHOI
  • Publication number: 20080255499
    Abstract: Disclosed herein are a composition for peritoneal dialysis comprising an ?-keto amino acid, and a method for peritoneal dialysis using the same. The composition allows peritoneal dialysis to be effected without the problems accompanying conventional compositions, including tissue toxicity and uremia.
    Type: Application
    Filed: November 17, 2006
    Publication date: October 16, 2008
    Applicant: RenoBiz Co ., Ltd
    Inventor: Bum-Seok Kim