Patents by Inventor Bum-Sik Jang
Bum-Sik Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953596Abstract: A light detection and ranging (lidar) device includes: a lower base; an upper base; a laser emitting unit for emitting a laser in a form of a point light source; a nodding mirror for transforming the laser in the form of the point light source to a line beam pattern which is perpendicular to the lower base, wherein the nodding mirror reflects the laser emitted from the laser emitting unit; a polygonal mirror for transforming the line beam pattern to a plane beam pattern and receiving a laser reflected from an object; and a sensor unit for receiving the laser reflected from the object via the polygonal mirror.Type: GrantFiled: September 21, 2022Date of Patent: April 9, 2024Assignee: SOS Lab Co., Ltd.Inventors: Ji Seong Jeong, Jun Hwan Jang, Dong Kyu Kim, Sung Ui Hwang, Gyeong Hwan Shin, Bum Sik Won
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Patent number: 9161479Abstract: Disclosed herein are a power module package and a method for manufacturing the same. According to a preferred embodiment of the present invention, a power module package includes: a metal substrate having an insulating layer and a circuit pattern formed on one surface thereof; at least one first electronic device mounted on the circuit pattern; a lead frame disposed around the metal substrate; a molding area enclosing the metal substrate, the first electronic device, and a portion of the lead frame; and a heat sink including a connection part contacting the insulating layer and a body part disposed on a surface opposite to the first electronic device and including one surface bonded to the connection part and the other surface exposed from an upper surface of the molding area.Type: GrantFiled: June 27, 2014Date of Patent: October 13, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Bum Sik Jang, Sung Min Song
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Publication number: 20150173246Abstract: Disclosed herein are a power module package and a method for manufacturing the same. According to a preferred embodiment of the present invention, a power module package includes: a metal substrate having an insulating layer and a circuit pattern formed on one surface thereof; at least one first electronic device mounted on the circuit pattern; a lead frame disposed around the metal substrate; a molding area enclosing the metal substrate, the first electronic device, and a portion of the lead frame; and a heat sink including a connection part contacting the insulating layer and a body part disposed on a surface opposite to the first electronic device and including one surface bonded to the connection part and the other surface exposed from an upper surface of the molding area.Type: ApplicationFiled: June 27, 2014Publication date: June 18, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Bum Sik Jang, Sung Min Song
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Publication number: 20150146382Abstract: Disclosed herein are a package substrate, a method of manufacturing the same, and a power module package using the package substrate.Type: ApplicationFiled: July 15, 2014Publication date: May 28, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Bum Sik Jang, Sung Min Song
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Publication number: 20140027049Abstract: There is provided a chip ejector including a fixing unit; and at least one or more conveying units disposed outwardly of the fixing unit, wherein the conveying units fall with a tape having one surface attached to upper portions of the conveying units, and separate a chip attached to the other surface of the tape therefrom.Type: ApplicationFiled: September 14, 2012Publication date: January 30, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Hui JOO, Sung Keun PARK, Kyung Sun JWA, Jung Mi OH, Bum Sik JANG
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Patent number: 8575756Abstract: Disclosed herein are a power package module and a method for fabricating the same, including: a base substrate; a plurality of high power chips and a plurality of low power chips electrically connected to the base substrate; and a plurality of metal lead plates electrically connecting the plurality of high power chips and the plurality of low power chips to the base substrate.Type: GrantFiled: June 1, 2011Date of Patent: November 5, 2013Assignee: Samsung Electro-Mechanics Co., LtdInventor: Bum Sik Jang
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Patent number: 8309399Abstract: Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.Type: GrantFiled: September 27, 2011Date of Patent: November 13, 2012Assignee: Samsung Electro-Mechanics Co., LtdInventors: Shan Gao, Seog Moon Choi, Tae Hyun Kim, Ju Pyo Hong, Bum Sik Jang, Ji Hyun Park
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Publication number: 20120273116Abstract: Disclosed herein is a heat dissipating substrate having a structure in which two two-layered core substrates, each including a metal core functioning to radiate heat, are laminated and connected in parallel to each other, thus accomplishing more improved radiation performance, and a method of manufacturing the same.Type: ApplicationFiled: June 28, 2012Publication date: November 1, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Young Ho SOHN, Seog Moon CHOI, Sung Keun PARK, Young Ki LEE, Bum Sik JANG, Ji Hyun PARK
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Publication number: 20120104621Abstract: Disclosed herein are a power package module and a method for fabricating the same, including: a base substrate; a plurality of high power chips and a plurality of low power chips electrically connected to the base substrate; and a plurality of metal lead plates electrically connecting the plurality of high power chips and the plurality of low power chips to the base substrate.Type: ApplicationFiled: June 1, 2011Publication date: May 3, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Bum Sik Jang
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Publication number: 20120015484Abstract: Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.Type: ApplicationFiled: September 27, 2011Publication date: January 19, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Shan GAO, Seog Moon CHOI, Tae Hyun KIM, Ju Pyo HONG, Bum Sik JANG, Ji Hyun PARK
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Patent number: 8058722Abstract: Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.Type: GrantFiled: August 31, 2009Date of Patent: November 15, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Shan Gao, Seog Moon Choi, Tae Hyun Kim, Ju Pyo Hong, Bum Sik Jang, Ji Hyun Park
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Patent number: 8017437Abstract: A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.Type: GrantFiled: December 1, 2009Date of Patent: September 13, 2011Assignee: Samsung Electro—Mechanics Co., Ltd.Inventors: Do-Jae Yoo, Young-Do Kweon, Seog-Moon Choi, Bum-Sik Jang, Tae-Sung Jeong
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Publication number: 20110031608Abstract: Disclosed is a power device package, which has high heat dissipation performance and includes an anodized metal substrate including a metal plate having a cavity formed on one surface thereof and an anodized layer formed on both the surface of the metal plate and the inner wall of the cavity and a circuit layer formed on the metal plate, a power device mounted in the cavity of the metal plate so as to be connected to the circuit layer, and a resin sealing material charged in the cavity of the metal plate. A method of fabricating the power device package is also provided.Type: ApplicationFiled: September 18, 2009Publication date: February 10, 2011Inventors: Tae Hyun KIM, Seog Moon Choi, Tae Hoon Kim, Bum Sik Jang, Ji Hyun Park
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Patent number: 7875983Abstract: A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate.Type: GrantFiled: December 1, 2009Date of Patent: January 25, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Do-Jae Yoo, Young-Do Kweon, Seog-Moon Choi, Bum-Sik Jang, Tae-Sung Jeong
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Patent number: 7875497Abstract: A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming a cavity by etching a center portion of a metal oxide layer; mounting a second chip inside the cavity; forming at least one via such that the via penetrates an edge of the metal oxide layer; placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon.Type: GrantFiled: December 1, 2009Date of Patent: January 25, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Do-Jae Yoo, Young-Do Kweon, Seog-Moon Choi, Bum-Sik Jang, Tae-Sung Jeong
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Publication number: 20110012252Abstract: Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.Type: ApplicationFiled: August 31, 2009Publication date: January 20, 2011Inventors: Shan GAO, Seog Moon Choi, Tae Hyun Kim, Ju Pyo Hong, Bum Sik Jang, Ji Hyun Park
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Publication number: 20100295172Abstract: Disclosed is a power semiconductor module having improved heat dissipation performance, including an anodized metal substrate including a metal plate, an anodized layer formed on a surface of the metal plate, and a circuit layer formed on the anodized layer on the metal plate, a power device connected to the circuit layer, and a housing mounted on the metal plate and for defining a sealing space which accommodates a resin sealing material for sealing the circuit layer and the power device.Type: ApplicationFiled: August 7, 2009Publication date: November 25, 2010Inventors: Shan Gao, Seog Moon Choi, Do Jae Yoo, Tae Hyun Kim, Bum Sik Jang, Ji Hyun Park
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Publication number: 20100294543Abstract: Disclosed herein is a heat dissipating substrate having a structure in which two two-layered core substrates, each including a metal core functioning to radiate heat, are laminated and connected in parallel to each other, thus accomplishing more improved radiation performance, and a method of manufacturing the same.Type: ApplicationFiled: August 11, 2009Publication date: November 25, 2010Inventors: Young Ho Sohn, Seog Moon Choi, Sung Keun Park, Young Ki Lee, Bum Sik Jang, Ji Hyun Park
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Publication number: 20100087034Abstract: A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming a cavity by etching a center portion of a metal oxide layer; mounting a second chip inside the cavity; forming at least one via such that the via penetrates an edge of the metal oxide layer; placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon.Type: ApplicationFiled: December 1, 2009Publication date: April 8, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Do-Jae Yoo, Young-Do Kweon, Seog-Moon Choi, Bum-Sik Jang, Tae-Sung Jeong
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Publication number: 20100087035Abstract: A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon.Type: ApplicationFiled: December 1, 2009Publication date: April 8, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Do-Jae Yoo, Young-Do Kweon, Seog-Moon Choi, Bum-Sik Jang, Tae-Sung Jeong