Abstract: Image sensors using multiple-ramp single slope analog to digital converters (ADCs) and method of their operation are disclosed. The images sensors use additional column ADCs to detect offset errors in the fine ramp signals and feedback in the analog domain to correct the errors. Averaging errors over multiple analog-to-digital conversion cycles allows for improved error correction.

Abstract: The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage.

Abstract: The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: A high-speed unity-gain input buffer steers the current that flows down a first path to an output node, and down a second path in response to an analog input signal. The current that flows down the second path is mirrored to sink a current out of the output node.

Abstract: A method for calibrating a capacitor mismatch error between a sampling capacitor and a feedback capacitor in a switched capacitor circuit includes sampling a fixed input voltage onto the sampling capacitor during a sampling phase of the switched capacitor circuit; placing the switched capacitor circuit in a hold/amplification phase of the switched capacitor circuit; providing a pair of level shift voltages alternately to the first plate of the sampling capacitor; generating a pair of output voltages at an output terminal of an amplifier where the pair of output voltages are a function of the sampled fixed input voltage, amplified by the amplifier and level shifted by the pair of level shift voltages and the pair of output voltages resemble output voltages in normal operation of the switched capacitor circuit; and comparing the pair of output voltages with respective corresponding ideal output voltages values to determine the capacitor mismatch error.

Abstract: An analog sampling network (100) includes a sampling capacitor being coupled between a bottom plate sampling switch and a top plate sampling switch implemented as NMOS transistors. The top plate sampling switch has source/drain terminals coupled respectively to the sampling capacitor and a first reference voltage. The analog sampling network includes a top plate boosting circuit (150) providing a boosted gate voltage to a gate terminal of the top plate sampling switch during a sampling phase, the boosted gate voltage being the sum of a first voltage and a second voltage. The first voltage is approximately equal to the first reference voltage and tracks process, temperature, power supply voltage and biasing condition variations. The second voltage is a maximum operating voltage from the gate to drain/source terminal for a fabrication process used to fabricate the second MOS transistor.

Abstract: A gain-boosted telescopic amplifier (100) includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (MP1, MN1), a pair of NMOS gain-boosted cascode transistors (MP2, MN2) and a pair of PMOS gain-boosted cascode transistors (MP3, MN3). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.

Abstract: A duty cycle stabilizer circuit (50) receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator (52) and a pulse width extender circuit (54). The pulse generator generates a first clock pulse (V1) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V2) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer (64) providing the output clock signal having the first duty cycle, a charge pump (56) receiving the output clock signal directly and a differential amplifier (62) generating an output signal for controlling the pulse width of the first and second clock pulses.

Abstract: A boosted voltage generator circuit includes a precharge voltage generator circuit and a first capacitor. The precharge voltage generator circuit receives a first DC voltage and a first power supply voltage and generates a precharge voltage having a first voltage value. The precharge voltage is inversely proportional to variations in the first power supply voltage. The first capacitor is connected between the precharge voltage node and the second power supply voltage during a first phase to be precharged to the precharge voltage and the first capacitor is connected between the boosted voltage output node and the first power supply voltage during a second phase to apply a boosted voltage at the boosted voltage output node where the boosted voltage has a voltage value being the sum of the precharge voltage and the first power supply voltage.

Abstract: A reference voltage generator that may be useful in analog-to-digital converter (ADC) circuits includes compensation for errors such as from non-ideal considerations such as semiconductor processing variations, mismatch errors, temperature gradients, and parasitic effects. The compensation method employs a correction current that is provided to the reference voltage generator to adjust the delay time and stability of the resulting reference voltage or voltages.

Abstract: Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.

Abstract: An oversaturation protection circuit is provided within a CMOS image sensor. A detector is arranged to monitor an output column line that is associated with a pixel to determine whether the pixel is oversaturated after being reset. If the pixel is oversaturated after being reset, the level of the pixel is determined by measuring the difference between a first reference voltage and the integrated voltage of the pixel. If the pixel is not oversaturated after being reset, the level of the pixel is determined by measuring the difference between the voltage of the column line shortly after reset and the integrated voltage of the pixel. A detector may be arranged to provide the result of the comparison of the associated pixel to be used with other pixels within the pixel column that are adjacent to the associated pixel.

Abstract: The present invention provides a method and apparatus for calibrating a black level in an imager to reduce flicker noise. A first and a second range is set. The first range corresponds to a range that is larger than a noise level at a highest PGA gain. The second range corresponds to a range that is smaller than a level which reduces an ADC dynamic range too much due to a large black level. The ranges may be adjusted to changes in an imager in real time. When the black level is within the second range a determination is made as to whether the black level has been calibrated before. When it has, the DAC output is held constant. Otherwise the DAC code is adjusted such that the black level is moved toward the first range. A small step size is used in adjusting the DAC code in order to reduce flicker. Step sizes may be adjusted according to the black level in relation to the ranges. A small step size is used when the black level is within the second range.

Abstract: An automatic exposure system is arranged to dynamically adjust the exposure time of a pixel array in an imaging system. A selected group of pixels from the pixel array are evaluated using a non-destructive readout procedure to determine the proper exposure time for the pixel array, while the pixel array is exposed to light that is reflected from a scene. Threshold detectors are employed to compare the signals from the selected group of pixels to a peak level that corresponds to a threshold limit for the pixels. The exposure of the pixel array is terminated when at least one pixel from the selected group of pixels exceeds the threshold limit. The threshold limit may be set to a level that is below total saturation for the pixels such that an overexposure margin is provided. Enhanced image contrast is achieved using automatic exposure time adjustment.

Abstract: DNL and INL errors are minimized in a pipelined converter that is arranged to use reference pre-sampling. An example first stage in the pipelined converter includes a sample/hold amplifier (SHA) circuit, an evaluator circuit, and a multiplying digital-to-analog converter (MDAC) circuit. The evaluator circuit evaluates the input signal in the converter while the SHA circuit samples the input signal. The MDAC samples the SHA output at substantially the same time it samples a reference voltage, where the reference voltage is adjusted in response to the output of the evaluator circuit. Errors due to capacitor mismatching are minimized such that the settling characteristics of the various amplifiers in the circuits dominate the DNL/INL performance.

Abstract: A charge-pump circuit generates a constant voltage higher than the available power supply. A feedback path maintains the voltage at a constant level in spite of power supply, temperature and process variations. This charge pump circuit includes a switched capacitor interface arranged to generate a target voltage that is used to activate and deactivate a bypass capacitor interface to maintain the constant voltage. The bypass capacitor interface is configured to complete the feedback path. The feedback helps to ensure that node n1, that is coupled to the output of the charge pump, stays at a constant potential, irrespective of the power supply voltage.

Abstract: A method and apparatus for system offset calibration using an overranging ADC is provided. The overranging ADC is configured to convert an analog signal into an intermediary digital signal. The conversion range of the overranging ADC is extended beyond the full dynamic range of the ADC system. The intermediary digital signal has more bits than the digital output signal. A digital fine offset adjustment circuit is configured to provide the digital output signal by digitally subtracting a fine offset from the intermediary digital signal and decoding the intermediary digital signal. The digital output signal has approximately no offset, and has approximately no loss in dynamic range.

Abstract: A switched capacitor amplifier provides high gain and wide bandwidth using dynamic loading. Dynamic loading is used to reduce the capacitive load during a high gain phase (e.g., during a sampling phase) and to increase the capacitive loading during a high feedback factor phase (e.g., during a holding phase). The capacitive load may be provided by an external capacitive load such as a sampling capacitor of a subsequent stage or sampling device. A low feedback factor provides a high voltage gain and the lower capacitive load. A high feedback factor increases the effective bandwidth of the amplifier by compensating for a unit gain bandwidth reduction that is due to high capacitive loading.