Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or less.

Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, and an electrode structure which is formed on the conductive plug.

Abstract: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or more.

Abstract: A ferroelectric capacitor in which damage caused by etching exposed faces of a ferroelectric layer of the capacitor is compensated by depositing a seeding layer of ferroelectric material such as PZT on one or more exposed faces of the ferroelectric layer and depositing an electrode layer made of conductive material such as platinum on the seeding layer. An oxygen annealing recovery process is applied to the device. The seeding layer can transform the phase of the damaged surfaces from amorphous to crystalline during the recovery annealing process and, at the same time, provide the damaged surfaces of the ferroelectric layer with missing element(s), for example lead. The oxygen necessary for recovery of the damage may be obtained through the platinum layer from the oxygen atmosphere.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, and an electrode structure which is formed on the conductive plug.

Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.

Abstract: A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer. A first bilayer or multi-layer seed structure is formed between the ferroelectric layer and either the first electrode layer or the second electrode layer.

Abstract: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.

Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.

Abstract: In a ferroelectic capacitor including a dielectric ferroelectric element sandwiched between a bottom electrode and top electrode, the bottom electrode is formed with a ridged structure, and the ferroelectric layer is formed over it and on its sides. Thus the dielectric between the top and bottom electrodes includes not just horizontal sections but also non-horizontal sections. The inventive structure thus has a higher effective capacitor area compared to the overall area of the device. This has two advantages. Firstly, it means that the total charge which can be stored in the device is higher. Secondly, it means that damage to the electrodes and the ferroelectric element at their edges regions occupies a lower proportion of the effective area of the device. The ridged structure of the bottom electrode may be due to it being formed over a ridged substructure, or because it is itself selectively etched.

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.