Abstract: A data storage device and a data processing system having the same are disclosed. The data storage device includes a nonvolatile memory and a controller, coupled to the nonvolatile memory, configured to receive first and second commands generated by a host and control an operation of the nonvolatile memory in response to the first command. The controller includes a core configured to receive and process the first command, a trace circuit corresponding to the core and configured to generate and output first data, based on pieces of information generated while the core processes the first command, and a trace controller configured to control output of the first data and second data differing from the first data, based on a result of performing at least one authentication control operation corresponding to the second command.

Abstract: A data storage device and a data processing system having the same are disclosed. The data storage device includes a nonvolatile memory and a controller, coupled to the nonvolatile memory, configured to receive first and second commands generated by a host and control an operation of the nonvolatile memory in response to the first command. The controller includes a core configured to receive and process the first command, a trace circuit corresponding to the core and configured to generate and output first data, based on pieces of information generated while the core processes the first command, and a trace controller configured to control output of the first data and second data differing from the first data, based on a result of performing at least one authentication control operation corresponding to the second command.

Abstract: Disclosed is a solid state disk including a storage unit configured to store data, and a control part configured to control enciphering and writing operation for the data using a key value and an initialization vector. The initialization vector is generated by processing an address corresponding to the data.

Abstract: A method of storing write data in flash memory incorporated in a storage device, the method includes; receiving write data and a logical block address (LBA) for the flash memory, determining whether the LBA exists in the cache memory, if the LBA exists in the cache memory, comparing the write data with cache data stored in the cache memory at a location associated with the LBA, and if the write data and the cache data are the same, terminating operation of the storage device without programming the write data to the flash memory, else updating an error detection information lookup table entry associated with the LBA and programming the write data to the flash memory, and if the LBA does not exist in the cache memory, updating the error detection information lookup table entry associated with the LBA and programming the write data to the flash memory.

Abstract: A storage apparatus including a storage unit to store data, a processor unit to process the data according to a command received from an external device, a key unit to store a plurality of crypto keys, and a decoder unit to select one of the crypto keys according to address information of the command received from the external device. Hardware encryption is more secure and less complex to manage.

Abstract: A method of detecting an error in write data includes generating first error detection data based on first write data to be written to a buffer memory, generating second error detection data based on second write data related with the first write data, comparing the first error detection data with the second error detection data, and generating an error detection signal according to a comparison result.

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Abstract: An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.

Abstract: Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to interpret a data command generated by a host hardware device.

Abstract: A storage apparatus including a storage unit to store data, a processor unit to process the data according to a command received from an external device, a key unit to store a plurality of crypto keys, and a decoder unit to select one of the crypto keys according to address information of the command received from the external device. Hardware encryption is more secure and less complex to manage.

Abstract: A method of storing write data in flash memory incorporated in a storage device, the method includes; receiving write data and a logical block address (LBA) for the flash memory, determining whether the LBA exists in the cache memory, if the LBA exists in the cache memory, comparing the write data with cache data stored in the cache memory at a location associated with the LBA, and if the write data and the cache data are the same, terminating operation of the storage device without programming the write data to the flash memory, else updating an error detection information lookup table entry associated with the LBA and programming the write data to the flash memory, and if the LBA does not exist in the cache memory, updating the error detection information lookup table entry associated with the LBA and programming the write data to the flash memory.

Abstract: An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Abstract: Provided are an encryption/decryption device and a security storage device including same. The encryption/decryption device includes a first enc/decrypter, a second enc/decrypter, a controller configured to provide a plurality of control signals in response to a setting signal, and a path selection circuit configured to connect the first enc/decrypter and the second enc/decrypter in either a series arrangement or a parallel arrangement in response to a first control signal among the plurality of control signals.

Abstract: Disclosed is a solid state disk including a storage unit configured to store data, and a control part configured to control enciphering and writing operation for the data using a key value and an initialization vector. The initialization vector is generated by processing an address corresponding to the data.

Abstract: The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the input signal is synchronized with a transition of a second clock. then, the synchronizing circuit generates an output signal synchronized with the transition of the second clock. In addition, an input signal synchronized with the first clock becomes synchronized with the second clock having a lower frequency than the first clock.

Abstract: A flash memory device includes a flash memory, a buffer memory and a control unit. The buffer memory temporarily stores data that is to be stored in the flash memory or data that is read from the flash memory. The control unit includes a buffer controller. The buffer controller performs a jump operation for transferring data unnecessary to be updated in the flash memory to an adjacent position of update data in the buffer memory when a size of data necessary to be updated in the flash memory is smaller than a size of a block of the flash memory. Therefore, the flash memory device and a flash memory system including the flash memory device may simplify an update operation with a DMA operation and a performance of a system is enhanced.

Abstract: Provided are a hybrid hard disk drive (HDD), a computer system including the hybrid HDD, and a flash memory DMA circuit for the hybrid HDD. The hybrid HDD includes a flash memory. The flash memory includes: a main memory region; and a spare memory region storing additional information necessary for transmitting user data stored in the main memory region. The flash memory DMA circuit of the hybrid HDD is used for interfacing the hybrid HDD with the flash memory. Therefore, rapid booting and low power consumption can be realized, while reducing overhead resulted from interfacing the hybrid HDD with the flash memory.

Abstract: Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to interpret a data command generated by a host hardware device.

Abstract: The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the input signal is synchronized with a transition of a second clock. Then, the synchronizing circuit generates an output signal synchronized with the transition of the second clock. In addition, an input signal synchronized with the first clock becomes synchronized with the second clock having a lower frequency than the first clock.