Abstract: In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel oxide layer may be formed on the active region of the substrate. A floating gate pattern may be formed on the tunnel oxide layer, and may include a lower part having a first width that is formed on the tunnel oxide layer and an upper part having a second width that is formed on the lower part, where the second width is substantially smaller than the first width. A dielectric layer pattern may be formed on the floating gate pattern, and a control gate pattern may be formed on the dielectric layer pattern. Accordingly, the non-volatile memory device may have an improved efficiency in programming and erasing data.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: Liquid crystal displays are manufactured by securing overlying first and second substrates with an intermediate sealant together such that they form a cell cavity with an injection opening. In one embodiment, a plurality of over-sized spacers are disposed intermediate the first and second substrates in the cell cavity. The first and second substrates are structurally secured by heat compressing the layers together with a pressure in the range of about 0.4-0.55 kg/cm.sup.2. A quantity of liquid crystal material is injected into the cell cavity through the injection opening to expand the substrate layers to a non-planar configuration. A second sealant is applied proximate to the injection opening and a second compressing step is used to facilitate the proper positioning of the second sealant into injection opening. The second compressing step employs a pressure about 0.1-1.0 kg/cm.sup.2 greater than the pressure in the first compressing step.