Patents by Inventor Bunshi Kuratomi
Bunshi Kuratomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8476113Abstract: When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly.Type: GrantFiled: June 15, 2011Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventors: Bunshi Kuratomi, Fukumi Shimizu
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Patent number: 8119050Abstract: Improvement in the yield of a semiconductor device is aimed at. When extruding a molded body with the ejector pin which performs advance-or-retreat movement at the projecting portion which projects from this bottom face in the bottom face of a mold cavity corresponding to the surface and the mounting side of a molded body after forming a molded body, depressed portions being formed in the surface and the mounting side by projecting portions, they can extrude. When accumulating molded bodies themselves in the baking step after a resin molding step and performing bake, by arranging the resin burr which furthermore withdrew from the surface and the mounting side in the depressed portion, bake can be performed in the condition that the accumulated molded bodies are stuck. Therefore, the form of deformation of a warp etc. of each molded body or a lead frame, can be made uniform, and, as a result, improvement in the yield of QFP (semiconductor device) is aimed at.Type: GrantFiled: July 25, 2005Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventors: Bunshi Kuratomi, Takafumi Nishita, Youichi Kawata
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Patent number: 8117742Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: GrantFiled: March 22, 2010Date of Patent: February 21, 2012Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu
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Publication number: 20120009737Abstract: When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly.Type: ApplicationFiled: June 15, 2011Publication date: January 12, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Bunshi KURATOMI, Fukumi SHIMIZU
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Publication number: 20100233857Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: ApplicationFiled: March 22, 2010Publication date: September 16, 2010Inventors: Bunshi KURATOMI, Fukumi Shimizu
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Patent number: 7681308Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: GrantFiled: May 9, 2008Date of Patent: March 23, 2010Assignees: Renesas Eastern Japan Semiconductor, Inc., Renesas Technology CorporationInventors: Bunshi Kuratomi, Fukumi Shimizu
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Patent number: 7632720Abstract: In connection with a memory card of a block molding type there is provided a method able to prevent the occurrence of a chip crack in transfer molding. The method includes a first step wherein a substrate having plural chips constituting plural memory cards and mounted on a surface of the substrate and further having connecting terminals in recesses formed on a substrate surface opposite to the chips-mounted surface is sandwiched between a first die (upper die) installed on the chips-mounted surface side and a second die (lower die) installed on the surface side where the connecting terminal are formed. The method further includes a second step of injecting sealing resin between the first die and the substrate to seal at a time the plural chips mounted on the substrate. Projecting portions (terminal supporting elements) projecting from the surrounding portion are formed in regions of the second die which regions are positioned just under the connecting terminals.Type: GrantFiled: July 31, 2006Date of Patent: December 15, 2009Assignee: Renesas Technology Corp.Inventors: Bunshi Kuratomi, Fukumi Shimizu
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Publication number: 20090160084Abstract: A lead frame is equipped between an upper die with which a gate port and an air vent part are not formed in a cavity part 12a and a lower die in which a gate port 15f is formed in one place of a corner of a cavity part 15a and an air vent part is not formed. After decompressing the inside of the die formed of the cavity parts 12a and 15a by clamping the upper die and the lower die with the clamp pressure of intermediate pressure, mold resin is allowed to flow in the die. Residual air is exhausted while allowing mold resin to flow in the die formed of the cavity parts 12a and 15a by once clamping the upper die and the lower die with low-pressure clamp pressure. Then, the mold resin which filled up in the die formed of the cavity parts 12a and 15a is formed by clamping the upper die and the lower die with high-pressure clamp pressure.Type: ApplicationFiled: December 28, 2006Publication date: June 25, 2009Inventors: Bunshi Kuratomi, Fukumi Shimizu, Takafumi Nishita
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Publication number: 20090004779Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: ApplicationFiled: May 9, 2008Publication date: January 1, 2009Inventors: Bunshi Kuratomi, Fukumi Shimizu
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Patent number: 7445969Abstract: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.Type: GrantFiled: October 29, 2007Date of Patent: November 4, 2008Assignee: Renesas Technology Corp.Inventors: Bunshi Kuratomi, Takafumi Nishita, Fukumi Shimizu
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Publication number: 20080173995Abstract: There is a need to provide a large capacity memory card for a portable communication device. A memory card 1 includes: a wiring board 2 mainly composed of a glass epoxy resin; multiple semiconductor chips (3C and 3F) mounted on a main surface of the memory card 1; and a mold resin 4 for encapsulating the wiring board 2 and the semiconductor chips (3C and 3F). The mold resin 4 is made of a thermosetting epoxy resin containing quartz filler. A back surface of the wiring board 2 is not covered with the mold resin 4 and is exposed to a back surface of the memory card 1. The back surface of the wiring board 2 is used to form multiple external connection terminals 7 electrically connected to the semiconductor chips (3C and 3F) . When the memory card 1 is attached to a card slot of a mobile phone, the external connection terminals 7 contact with a connector terminal contained in the card slot. This makes it possible to exchange signals between the memory card 1 and the mobile phone or to supply the power.Type: ApplicationFiled: September 12, 2007Publication date: July 24, 2008Inventors: Bunshi Kuratomi, Fukumi Shimizu, Michiaki Sugiyama, Atsushi Fujishima, Tamaki Wada
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Patent number: 7377031Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: GrantFiled: December 30, 2005Date of Patent: May 27, 2008Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu
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Publication number: 20080057626Abstract: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.Type: ApplicationFiled: October 29, 2007Publication date: March 6, 2008Inventors: Bunshi KURATOMI, Takafumi Nishita, Fukumi Shimizu
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Publication number: 20080020510Abstract: A technique able to effect automation of a molding process corresponding to a multifarious small lot semiconductor device manufacturing process is provided. As to a frame supply unit, a lead frame conveying unit and molding press sets, which are each operated by a motor within a molding apparatus, the amount of operation of the motor is controlled in accordance with preset data so as to give an amount of operation matching the size of a lead frame. When the type of the lead frame changes, the data concerned is read and the amount of the operation of the motor is switched automatically.Type: ApplicationFiled: July 18, 2007Publication date: January 24, 2008Inventors: Bunshi Kuratomi, Fukumi Shimizu, Yoichi Kawata
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Patent number: 7288440Abstract: For molding semiconductor chips on a wiring substrate matrix with a sealing resin, the wiring substrate matrix is placed on a lower die cavity block of a lower die, and, thereafter, an upper die is brought down, whereby an outer peripheral portion of a cavity of the upper die comes into abutment against an outer peripheral portion of a main surface of the wiring substrate matrix, causing the substrate matrix to be deformed a sufficient extent to prevent resin leakage. Thereafter, block pins provided on the upper die push down the lower die cavity block. Thus, when clamping the wiring substrate matrix using both upper and lower dies, it is possible to suppress or prevent the application of excessive pressure to the wiring substrate matrix and to suppress or prevent deformation or cracking caused by crushing of the wiring substrate matrix. Consequently, the semiconductor device manufacturing yield can be improved.Type: GrantFiled: September 23, 2004Date of Patent: October 30, 2007Assignee: Renesas Technology Corp.Inventors: Bunshi Kuratomi, Takafumi Nishita, Fukumi Shimizu
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Publication number: 20070057379Abstract: In connection with a memory card of a block molding type there is provided a method able to prevent the occurrence of a chip crack in transfer molding. The method includes a first step wherein a substrate having plural chips constituting plural memory cards and mounted on a surface of the substrate and further having connecting terminals in recesses formed on a substrate surface opposite to the chips-mounted surface is sandwiched between a first die (upper die) installed on the chips-mounted surface side and a second die (lower die) installed on the surface side where the connecting terminal are formed. The method further includes a second step of injecting sealing resin between the first die and the substrate to seal at a time the plural chips mounted on the substrate. Projecting portions (terminal supporting elements) projecting from the surrounding portion are formed in regions of the second die which regions are positioned just under the connecting terminals.Type: ApplicationFiled: July 31, 2006Publication date: March 15, 2007Inventors: Bunshi Kuratomi, Fukumi Shimizu
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Patent number: 7176060Abstract: A multi-function structure of a plug-in universal IC card is to be promoted and the manufacturing cost is to be reduced. The body of the plug-in UICC is constructed of a molding resin. A tape substrate and a chip mounted on one side of the tape substrate are sealed in the interior of the molding resin. A side opposite to the chip mounting side of the tape substrate is exposed to the exterior of the molding resin and constitutes a surface portion of the plug-in UICC. Contact patterns serving as external terminals of the plug-in UICC are formed on the surface of the tape substrate exposed to the exterior of the molding resin. In the plug-in UICC whose body is constructed of molding resin, cracking of the chip can be prevented effectively even in the case where the chip is large-sized.Type: GrantFiled: July 30, 2004Date of Patent: February 13, 2007Assignee: Renesas Technology Corp.Inventors: Nobuaki Yamada, Kazunari Suzuki, Bunshi Kuratomi, Hiroaki Tanaka, Akira Onozawa
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Patent number: 7144755Abstract: At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.Type: GrantFiled: August 19, 2004Date of Patent: December 5, 2006Assignees: Renesas Technology Corp., Eastern Japan Semiconductor Technologies, Inc.Inventors: Bunshi Kuratomi, Fukumi Shimizu, Kenichi Imura, Katsushige Namiki, Fumio Murakami
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Publication number: 20060216867Abstract: In the manufacture of a semiconductor device, a molding die is used having a resin sealing member forming section positioned over the main surface of a wiring substrate so as to cover a semiconductor chip mounted on the wiring substrate, and a resin flowing path crossing one side of the wiring substrate from the outside of the wiring substrate and communicating with the resin sealing member forming section, when the wiring substrate is arranged between an upper die and a lower die. A method of manufacturing a semiconductor device includes a step of forming a resin sealing member, that seals the semiconductor chip mounted on the wiring substrate with resin, by injecting resin into the resin sealing member forming section through the resin flowing path. The resin flowing path has a first portion positioned at the outside of the wiring substrate and a second portion communicating with the first portion and the resin sealing member forming section and positioned over the main surface of the wiring substrate.Type: ApplicationFiled: March 2, 2006Publication date: September 28, 2006Inventors: Youichi Kawata, Bunshi Kuratomi
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Publication number: 20060105504Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.Type: ApplicationFiled: December 30, 2005Publication date: May 18, 2006Inventors: Bunshi Kuratomi, Fukumi Shimizu