Patents by Inventor Bunshiro Yamaki

Bunshiro Yamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5283459
    Abstract: A semiconductor sensor with a compact structure is provided, which comprises a semiconductor substrate, a semiconductor diaphragm integrally formed with the semiconductor substrate, and a penetrating aperture formed in the semiconductor substrate so as to surround desired sides of the diaphragm. The aperture has first and second funnel-shaped aperatures whose intersecting conic sections open toward opposite directions. A cavity for defining the diaphragm is provided when the semiconductor substrate is subjected to electrolytic etching to form the second funnel-shaped aperture therein.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: February 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Hirano, Bunshiro Yamaki
  • Patent number: 5238850
    Abstract: A Bi-MOS type semiconductor integrated circuit device having at least one bipolar transistor in an island region is provided. The island region is covered with a multilayer insulating film which is formed of a silicon oxide film and a silicon nitride film having a different etching resistance with each other. Collector and base contact holes and an intended emitter contact hole are formed in the multilayer insulating film at the same time to provide bipolar transistors having a fine structure. An insulated gate MOS transistor includes a protective film such as polysilicon film covering a gate insulating film to increase the reliability.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Bunshiro Yamaki
  • Patent number: 5212398
    Abstract: In an integrated circuit device including a bipolar transistor, MOSFET, and protective diode for the MOSFET, all formed over a semiconductor substrate, the protective diode for holding an adequate electrostatic breakdown voltage for a gate oxide layer of the MOSFET is provided by forming a second conductivity type buried area continuous with, and in contact with, a second conductivity type region at a boundary between the first conductivity type semiconductor substrate and a first conductivity type second semiconductor layer. By doing so, a substantive junction depth Xj is made deeper as a whole with respect to the second conductivity type region. It is, therefore, possible to obtain a protective diode of adequate electrostatic breakdown-voltage characteristic which does not adversely affect the operation of the MOSFET even if a relatively thin semiconductor layer is employed.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Matsunaga, Bunshiro Yamaki
  • Patent number: 5100812
    Abstract: According to a method of manufacturing a high-frequency bipolar transistor, a p-type base region is formed on an n-type silicon substrate. A first oxide film and a nitride film are formed on the base region. A base contact hole is formed by etching, and a first polysilicon film containing a p-type impurity and serving as a base electrode is formed thereon. A second oxide film having a thickness larger than that of the first oxide film is formed by thermal oxidation around the base contact hole to surround the first polysilicon film. A portion of the nitride film which is not covered with said second oxide film and a portion of the first oxide film therebelow are removed by etching to form an emitter contact hole. A second polysilicon film including an n-type impurity and serving as an emitter electrode is formed in the emitter contact hole. The n-type impurity in the second polysilicon film is diffused in the substrate by annealing to form an n-type emitter region.
    Type: Grant
    Filed: December 11, 1990
    Date of Patent: March 31, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiki Yamada, Bunshiro Yamaki
  • Patent number: 5021859
    Abstract: In a high-frequency amplifying semiconductor device in which a MOS field effect transistor and a bipolar transistor are formed within the same wafer and a source electrode of the MOS field effect transistor is connected to a lead frame by a bonding wire, use is made of a wafer for fabricating the MOS field effect transistor and the bipolar transistor, in which on a semiconductor substrate of P++ type is formed a first epitaxial layer of P or P- type, a buried layer of N+ type is formed in the first epitaxial layer of the first conductivity type and a second epitaxial layer of P type is formed on the buried layer and the first epitaxial layer. The use of such a wafer, which has no P- type Si substrate, allows the source resistance of the MOS field effect transistor to be decreased. The high-frequency amplifying semiconductor device is improved in high-frequency gain and NF.
    Type: Grant
    Filed: November 9, 1989
    Date of Patent: June 4, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Ito, Bunshiro Yamaki, Yoshio Yamamoto
  • Patent number: 4962056
    Abstract: According to the method of the present invention of manufacturing, from a semiconductor wafer, a dielectric substrate including insulated and separated island regions, a silicon oxide film is formed on a surface of a monocrystalline semiconductor wafer, and a mask consisting of a frame portion spreading on a peripheral region of the wafer and a grid-like portion arranged within the frame portion is formed. Then, in a patterning step, the surface of the wafer is exposed with the frame portion and the grid-like portion of the mask being left. Separation grooves arranged in a grid-like manner are formed in the exposed surface by etching. After a silicon oxide film is formed on the surfaces of the grooves, a polycrystalline semiconductor layer is made to grow on the silicon oxide film formed on the surfaces of the grooves and on the silicon oxide film formed on the surface of the wafer.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: October 9, 1990
    Assignee: Kabushiki Kaishi Toshiba
    Inventors: Bunshiro Yamaki, Nobutaka Matsuoka
  • Patent number: 4680569
    Abstract: A semiconductor pressure sensor wherein a semiconductor chip of diaphragm type is supported by a mount plate through a thin tubular supporting member or a pressure inlet tube having a coefficient of thermal expansion similar to that of a substrate constituting the semiconductor chip. The semiconductor chip is fixed to the thin tubular supporting member or the pressure inlet tube by means of a bonding material, and the thin tubular supporting member or the pressure inlet tube is fixed by means of a bonding material having a high bonding strength with respect thereto, thus absorbing thermal stress produced due to the difference in coefficient of thermal expansion.
    Type: Grant
    Filed: September 27, 1984
    Date of Patent: July 14, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Bunshiro Yamaki, Sadatake Kikuchi, Yutaka Tomisawa