Abstract: The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

Abstract: A semiconductor integrated circuit comprises a plurality of memory cell blocks each including a comparing cell which detects a current level and data cells which store data therein, a plurality of reference voltage determining circuits each of which determines a second reference voltage in accordance with a first reference voltage and the output of the comparing cell, and amplifiers each of which compares the data stored in the data cell and the output of the reference voltage determining circuit and amplifies the result of comparison. The outputs of the comparing cells are short-circuited in a predetermined combination. Owing to the configuration of the semiconductor integrated circuit, misdetection of each reading cell due to process variations related to each individual comparing cell can be prevented and yield enhancement can be achieved. Further, such a configuration leads to a cost reduction.

Abstract: A semiconductor integrated circuit comprises a plurality of memory cell blocks each including a comparing cell which detects a current level and data cells which store data therein, a plurality of reference voltage determining circuits each of which determines a second reference voltage in accordance with a first reference voltage and the output of the comparing cell, and amplifiers each of which compares the data stored in the data cell and the output of the reference voltage determining circuit and amplifies the result of comparison. The outputs of the comparing cells are short-circuited in a predetermined combination. Owing to the configuration of the semiconductor integrated circuit, misdetection of each reading cell due to process variations related to each individual comparing cell can be prevented and yield enhancement can be achieved. Further, such a configuration leads to a cost reduction.

Abstract: A substrate voltage generating circuit includes a first power supply node of a first potential level, a second power supply node of a second potential level lower than the first potential level, and an output node receiving a voltage having a third potential level lower than the second potential level. The circuit also includes a level shift circuit coupled between the first power supply node and the output node, receiving an input signal having the first and second potential levels, and outputting an output signal having the first potential level and the third potential level. The circuit also includes a switch circuit connecting the second power supply node to the output node in response to the output signal.

Abstract: The aim of the present invention is to provide a power supply control system which enables an improvement in the response speed of the voltage sensor section to be achieved at a low level of power consumption. The present invention comprises: a voltage booster circuit for boosting voltage; a voltage sensor section which operates on the basis of voltage output from the voltage booster circuit; and a threshold value altering circuit which lowers a threshold value of the voltage sensor section when the voltage booster circuit is operating, and raises a threshold value of the voltage sensor section when the operation of the voltage booster circuit is halted.