Patents by Inventor Buo-Chin Hsu
Buo-Chin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791217Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.Type: GrantFiled: May 3, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Patent number: 11245034Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: GrantFiled: April 25, 2018Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Ming Chang, Ta-Chun Lin, Rei-Jay Hsieh, Yung-Chih Wang, Wen-Huei Guo, Kuo-Hua Pan, Buo-Chin Hsu
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Publication number: 20210272852Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.Type: ApplicationFiled: May 3, 2021Publication date: September 2, 2021Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Patent number: 11037831Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: GrantFiled: January 8, 2020Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Patent number: 10998237Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: GrantFiled: April 20, 2020Date of Patent: May 4, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Publication number: 20200243396Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: ApplicationFiled: April 20, 2020Publication date: July 30, 2020Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Publication number: 20200144128Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Patent number: 10629492Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: GrantFiled: April 27, 2018Date of Patent: April 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Publication number: 20190334035Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Inventors: Kuei-Ming CHANG, Ta-Chun LIN, Rei-Jay HSIEH, Yung-Chih WANG, Wen-Huei GUO, Kuo-Hua PAN, Buo-Chin HSU
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Publication number: 20190333822Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
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Publication number: 20130171789Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Inventors: Ling-Chun Chou, Shin-Chuan Huang, I-Chang Wang, Ching-Wen Hung, Buo-Chin Hsu, Yi-Han Ye
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Patent number: 7588991Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.Type: GrantFiled: July 18, 2007Date of Patent: September 15, 2009Assignee: United Microelectronics Corp.Inventors: Tung-Hsing Lee, Chien-Li Kuo, Yun-San Huang, Chih-Ming Su, Buo-Chin Hsu
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Publication number: 20090023256Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.Type: ApplicationFiled: July 18, 2007Publication date: January 22, 2009Inventors: Tung-Hsing Lee, Chien-Li Kuo, Yun-San Huang, Chih-Ming Su, Buo-Chin Hsu
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Patent number: 6916674Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.Type: GrantFiled: November 12, 2003Date of Patent: July 12, 2005Assignee: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Buo-Chin Hsu, Chee-Wee Liu
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Publication number: 20040201009Abstract: An infrared photodetector formed of a MOS tunneling diode is disclosed. The infrared photodetector comprises a conducting layer, a semiconductor layer comprising at least one layer of quantum structure for confining a carrier in a barrier, an insulating layer formed between the conducting layer and the semiconductor layer, and a voltage source connected to the conducting layer and the semiconductor layer for providing a bias voltage to generate a quantum tunneling effect, such that the carrier penetrates through the insulating layer to form a current, wherein when irradiated by an infrared, the carrier in the barrier absorbs the energy of the infrared to jump out of the barrier and is collected by an electrode to form a photocurrent.Type: ApplicationFiled: April 1, 2004Publication date: October 14, 2004Applicant: National Taiwan UniversityInventors: Buo-Chin Hsu, Shu-Tong Chang, Shi-Hao Huang, Chee-Wee Liu
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Publication number: 20040152225Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.Type: ApplicationFiled: November 12, 2003Publication date: August 5, 2004Applicant: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Buo-Chin Hsu, Chee-Wee Liu