Patents by Inventor Bu Qi Cheng

Bu Qi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compiler-based instruction scoreboarding
    Patent number: 10191724
    Abstract: Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to remove unnecessary dependence edges from a data dependency graph, partition the data dependency graph into a plurality of sub-graphs, determine a live range for each of the plurality of sub-graphs, and assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard entries. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 29, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bu Qi Cheng, Wei-Yu Chen, Guei-Yuan Lueh
  • COMPILER-BASED INSTRUCTION SCOREBOARDING
    Publication number: 20180113713
    Abstract: Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to remove unnecessary dependence edges from a data dependency graph, partition the data dependency graph into a plurality of sub-graphs, determine a live range for each of the plurality of sub-graphs, and assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard entries. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 26, 2018
    Applicant: Intel Corporation
    Inventors: Bu Qi Cheng, Wei-Yu Chen, Guei-Yuan Lueh
  • Statement shifting to increase parallelism of loops
    Patent number: 7770162
    Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventors: Li Liu, Zhaohui Du, Bu Qi Cheng, Shiwei Liao, Gansha Wu, Tin-fook Ngai
  • Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal
    Patent number: 7757222
    Abstract: Code is affine partitioned to generate affine partitioning mappings. Parallel code is generated based on the affine partitioning mappings. Generating the parallel code includes coalescing loops in the parallel code generated from the affine partitioning mappings to generate coalesced parallel code and optimizing the coalesced parallel code.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Shih-wei Liao, Zhao Hui Du, Bu Qi Cheng, Gansha Wu, Guei-Yuan Lueh