Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: Various embodiments for hyper-channel management are disclosed. One such method is implemented by a network interface controller (NIC) residing in a server. This method involves determining a network component that is operable to create, modify, terminate, or any combination thereof, a hyper-channel. The hyper-channel corresponds to a logical abstraction of network resources associated with the server. The method also involves using the determined network component to manage the hyper-channel.

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

Abstract: A server comprising a network interface controller (NIC) may be operable to determine network components and/or resources that may be utilized to create, modify and/or terminate a hyper-channel in a network fabric. A configuration for creating, modifying and/or terminating the hyper-channel may be initiated by the NIC based on knowledge of the network fabric up to the edge of network and each of the switches along a path of the hyper-channel may be instructed by the NIC to configure the hyper-channel. The configuration may also be initiated by the NIC based on knowledge of the network fabric up to a first hop and each of the switches along a path of the hyper-channel may then be allowed to configure the hyper-channel based on knowledge of the network fabric surrounding each of the switches.

Abstract: A single root I/O virtualization (SR-IOV) capable peripheral component interconnect (PCI) device may be operable to configure resources to transparently operate in a non-SR-IOV environment utilizing a physical function (PF) and one or more hybrid functions (HFs). In instances when the SR-IOV capable PCI device is operating in a SR-IOV environment, the SR-IOV capable PCI device may expose a VF configuration space in the hybrid function to an associated PCI driver for configuring the hybrid function as a virtual function. In instances when the SR-IOV capable PCI device is operating in a non-SR-IOV environment, the SR-IOV capable PCI device may hide a SR-IOV extended header in the physical function from the associated PCI driver and expose a PF configuration space in the hybrid function to the associated PCI driver for configuring the hybrid function as a physical function.

Abstract: A server comprising a network interface controller (NIC) may be operable to determine network components and/or resources that may be utilized to create, modify and/or terminate a hyper-channel in a network fabric. A configuration for creating, modifying and/or terminating the hyper-channel may be initiated by the NIC based on knowledge of the network fabric up to the edge of network and each of the switches along a path of the hyper-channel may be instructed by the NIC to configure the hyper-channel. The configuration may also be initiated by the NIC based on knowledge of the network fabric up to a first hop and each of the switches along a path of the hyper-channel may then be allowed to configure the hyper-channel based on knowledge of the network fabric surrounding each of the switches.

Abstract: A single root I/O virtualization (SR-IOV) capable peripheral component interconnect (PCI) device may be operable to configure resources to transparently operate in a non-SR-IOV environment utilizing a physical function (PF) and one or more hybrid functions (HFs). In instances when the SR-IOV capable PCI device is operating in a SR-IOV environment, the SR-IOV capable PCI device may expose a VF configuration space in the hybrid function to an associated PCI driver for configuring the hybrid function as a virtual function. In instances when the SR-IOV capable PCI device is operating in a non-SR-IOV environment, the SR-IOV capable PCI device may hide a SR-IOV extended header in the physical function from the associated PCI driver and expose a PF configuration space in the hybrid function to the associated PCI driver for configuring the hybrid function as a physical function.