Abstract: A system and process are disclosed for automatically resuming data communication using an IEEE-1394 PHY when communication is suspended because input bias is momentarily lost. The PHY determines whether data communication is suspended due to the PHY being disconnected from a network by checking the status of a connected flag. If the connected flag is still set to TRUE, the PHY was not intentionally disconnected from the network and it automatically attempts to resume communication by setting a resume flag to TRUE. The invention finds application in any type of communication device using the IEEE-1394 high-speed serial bus standard including audio and video sources, which may readily be connected to a personal computer for data storage or editing. The system and process may be implemented using software code and included within a digital signal processor (DSP).

Abstract: A system and process are disclosed for automatically resuming data communication using an IEEE-1394 PHY when communication is suspended because input bias is momentarily lost. The PHY determines whether data communication is suspended due to the PHY being disconnected from a network by checking the status of a connected flag. If the connected flag is still set to TRUE, the PHY was not intentionally disconnected from the network and it automatically attempts to resume communication by setting a resume flag to TRUE. The invention finds application in any type of communication device using the IEEE-1394 high-speed serial bus standard including audio and video sources, which may readily be connected to a personal computer for data storage or editing. The system and process may be implemented using software code and included within a digital signal processor (DSP).

Abstract: An IEEE 1394 serial bus (58) is interfaced utilizing a physical layer (54) to extract the data and a link/transaction layer controller (200) to interface the data from the physical layer (54) to a host system. The host system consists of a peripheral device (210) which is interfaced with various host buses (202). The link/transaction layer controller (200) is operable to emulate the microcontroller function such that addresses can be transmitted to the peripheral device (210) along with data, such that a remote node can access the peripheral device (210) by transmitting address and data information thereto. Alternatively, address and data information can be transmitted from the peripheral device (210) to the controller (200) which will process the received address and data and transmit it to a remote node.

Abstract: A physical layer (PHY) controller (314) for arbitrating and resetting a bus for devices coupled to a tri-stateable transceiver (316). The controller (314) includes a tri-stateable driver output enable pin (TDOE) and a novel arbitration scheme. A particular priority code and node address are used in the arbitration number used to arbitrate for the bus before resetting the bus.