Abstract: The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

Abstract: A DMA module is described which, in order to read or write a memory location within a DMA process, accesses by a reading operation a memory location of an addressable memory (5) identified by a first address (46) in order to read there at least one second address (52); which advances the second address (52) to an adjacent memory location, and implements a write access or read access at a memory location identified by the second address (52); and which finally stores the second address at the memory location identified by the first address (46).

Abstract: A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory location. The address counter does not act on an internal register of the DMA module but instead is configured so that between reading an address value from the memory and writing the address value to the memory, the address counter is advanced once. The memory location at which the address value is read or written takes on the function of a register conventionally integrated in the DMA module. This approach reduces the space requirement of the DMA module, and the DMA module may be employed to control a large number of DMA processes that may mutually interrupt each other by providing a plurality of memory locations to store specifications of the DMA blocks.

Abstract: A DMA module is described which, in order to read or write a memory location within a DMA process, accesses by a reading operation a memory location of an addressable memory (5) identified by a first address (46) in order to read there at least one second address (52); which advances the second address (52) to an adjacent memory location, and implements a write access or read access at a memory location identified by the second address (52); and which finally stores the second address at the memory location identified by the first address (46).

Abstract: Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

Abstract: A MOS driver circuit has a first output transistor and a second output transistor which are driven in push-pull into a conducting state by a first driver stage having first high impedance and first low impedance elements and a second driver stage having second high impedance and second low impedance elements, respectively. The high impedance driver elements drive the output transistors into a conducting or nonconducting state and the low impedance driver elements hold the output transistors in the nonconducting state. The junction of the output transistors can be connected to a load. A holding stage for each driver stage is cross coupled to a high impedance driver element of one output transistor and the low impedance driver element of the other output transistor, so as to drive one output transistor in the conducting state while holding the other output transistor in a nonconducting state. As a result, shunt currents between the output transistors are avoided even in the presence of output noise.

Abstract: The invention is a method and circuit for improving the settability of the output current (i1) of at least one pad driver (D: D1, D2, . . . Dn) to reduce interfering voltage dips on the supply lines. The pulselike current peaks caused by rapid charging/discharging of high load capacitances (c) are particularly avoided. To this end, the respective output transistor (t1, t1') is operated as a current-controlled element in a first range (b1) of the output voltage (OUR) and as a voltage-controlled element in a second range (b2).

Abstract: A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).

Abstract: A filter circuit is driven by two digital phase responsive output signals from the frequency/phase discriminator of a phase-locked loop (PLL) circuit. The controlled current paths of a first n-conducting transistor, a second n-conducting transistor, a second p-conducting transistor and a first p-conducting transistor are connected in that order between the plus and minus poles of a source of supply voltage. The common connection between the controlled current paths of the second n-conducting transistor and the second p-conducting transistor is connected to the output of the filter circuit.

Abstract: In this protective arrangement, a resistor between a pad (p) and a transistor to be protected is implemented with an expansion region (e) which lies completely below the pad (p) and extends beyond the latter along the entire circumference of the pad. An elongate region (z) extends along the circumference of the expansion region (e) and is connected to circuit ground via an interconnection track (b). The connection between the elongate region (z) and the interconnection track (b) has a low resistance.

Abstract: A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.

Abstract: In an integrated matrix of nonvolatile, reprogrammable storage cells, additional memory is provided to replace defective rows of storage cells. The addresses of the defective rows are stored in a region of the matrix. A correction register can be loaded with the addresses of the defective rows from the region of the matrix when power is first applied to the matrix or whenever the applied power deviates from the expected, nominal value.

Abstract: The circuit merely comprises three transistors, namely one transfer transistor (t) arranged between the input (e) and the output (a), a load transistor (l) connected as a resistor, and a clamping transistor (k), with both of the latter connecting the output (a) to the source of operating voltage (U). The interconnected gates of both the clamping and the transfer transistor (k, t) are connected to a source of reference voltage (Ur). If these two transistors (k, t) are of the depletion type, the two gates thereof may be connected to the zero point of the circuit. The circuit is particularly quick and simple.

Abstract: An integrated memory system includes a microcomputer which, at defined intervals and by employing a classifying circuit integrated in an EEPROM, checks the memory cells of the EEPROM with respect to variations of the threshold values. Upon detection of a fault in a row or column which has thus been recognized as being faulty, this faulty row or column whose address is then stored in one EEPROM area, is replaced by a redundant row or column in another area by making use of a correction register.

Abstract: An electrically programmable memory matrix comprises electrically programmable memory cells arranged in columns and rows, each consisting of a source-drain series arrangement of a memory transistor with a select transistor. The gate of the select transistor may be connected to one of row selecting lines of a row decoder, to which there are connected all gates of one row of the selected transistors of the memory cells of the same row. Control gates of groups of memory transistors (Ts) of one row may be connected to one common programming line, with these programming lines being connected by blocks via each time one group select transistor to one common block line which, via the source-drain line of a block select transistor whose gate is connected to one of a plurality of outputs of a block decoder is connected to one source of block signals.

Abstract: EEPROM showing storage cells comprising a tunnel injector which at the one hand is connected to a first bit line by means of the source-drain-line of a floating gate FET and at the other hand to a second bit line by means of the source-drain-line of a selection FET. Interferences between addressed groups and not addressed groups of storage cells during writing are eliminated by means of connection of the first bitline of the not addressed groups via the source-drain-lines of a depletion type FET and an enhancement FET to ground.

Abstract: The invention discloses an integrated memory matrix comprising nonvolatile reprogrammable storage (memory) cells arranged in rows and columns, as well as a classifying circuit integrated as well in the semiconductor body of the memory matrix, containing a nonprogrammable reference storage cell (Mr) of the same construction as that of the storage cells, and which is manufactured simultaneously as a comparison standard, with the storage cells. With the aid of a first voltage divider (Q1) integrated as well, whose output voltage is adjustable in steps, and whose output current is fed into the source-drain line of the reference storage cell (Mr) and/or of a second voltage divider (Q2) adjustable in steps and integrated as well, whose output voltage is applied to the control gate of the storage transistor (Ts) of the reference storage cell (Mr), it is possible to simulate a threshold voltage which is compared with the threshold voltages of the storage cells (M11 . . .

Abstract: An electrically programmable memory includes a test circuit usable for detection of interaction between adjacent memory cells by easily permitting a checkerboard-pattern to be programmed into the memory.

Abstract: Reprogrammable semiconductor read-only memory with memory cells of the floating-gate type, including an additional potential carrier for each memory cell for capacitively coupling a further potential to the floating gate.

Abstract: Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation.