Abstract: A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Abstract: A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.

Abstract: Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step with an isotropic component and the spacer structure comprises at least one point on the surface with a large solid angle opening towards the environment. Method of manufacturing an integrated circuit, including a regional removal of a spacer structure, wherein the removal is determined by a pattern density in the vicinity of the spacer structure.

Abstract: A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Abstract: A lithography mask has an angled structure element (O) formed by a first opaque segment (O1) and by a second opaque segment (O2). The structure element has at least one reflex angle (?). The angled structure element (O) includes at least one convex section (A) facing the reflex angle (?). At least one transparent structure (T) adjacent to the angled structure element (O) is provided at the convex section (A) of the angled structure element (O). The transparent structure (T) is formed in separated fashion at the convex section (A) of the angled structure element (O) and thus comprises two distinguishable transparent segments (T1, T2) formed at least in sections essentially axially symmetrically with respect to the angle bisector (WH) of the reflex angle.

Abstract: A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.

Abstract: A layout cell includes layout cell information including information about at least one component, and a layout cell identifier identifying the layout cell. The layout cell identifier includes geometrical information about the layout cell.

Abstract: A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts of the circuit pattern of the plurality of structural elements wherein there exists a match with the basic pattern. Subsequently, further basic patterns are determined for those parts of the circuit pattern which were not previously classified. After applying a specification for optimizing the geometry of the structural elements, the optimized basic patterns are inserted into the circuit design thus achieving an improvement of the optical imaging properties.

Abstract: In order to eliminate phase conflicts in alternating phase masks, the layout is modified after the phase conflicts have been localized. During the modification, degenerate critical structures, which fall below a minimum width and require phase-shifting regions for their adequate imaging, are widened, so that the phase-shifting regions directly adjoining the degenerate critical structures disappear. Moreover, interaction regions between phase-shifting regions can be eliminated by trimming masks, intermediate phases or shifting associated critical structures.

Abstract: A method is used to check the direct convertibility of integrated semiconductor circuits into alternating phase masks. This is done by explicitly localizing the phase conflicts occurring in the corresponding layout while solely using the technological requirements made of the design. The set of phase conflicts determined with the aid of this formalism is complete and minimal and thus proves to be an optimum starting point for methods for handling conflicts of this type.

Abstract: A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

Abstract: A lithography mask has an angled structure element (O) formed by a first opaque segment (O1) and by a second opaque segment (O2). The structure element has at least one reflex angle (?). The angled structure element (O) includes at least one convex section (A) facing the reflex angle (?). At least one transparent structure (T) adjacent to the angled structure element (O) is provided at the convex section (A) of the angled structure element (O). The transparent structure (T) is formed in separated fashion at the convex section (A) of the angled structure element (O) and thus comprises two distinguishable transparent segments (T1, T2) formed at least in sections essentially axially symmetrically with respect to the angle bisector (WH) of the reflex angle.

Abstract: A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network description as well as information about the instantiations. A raw data structure represents the logical configuration of the layout and associates each instantiation with one, and only one, polygon data structure. A modified data structure is produced to represent the layout, which associates a circuit network description with one, and only one, polygon data structure, wherein the geometrical differences between the instantiations of this circuit network description are taken into account by variants in the polygon data structure.

Abstract: A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation that is phase-shifted by 180°. The first and second sections adjoin one another in boundary regions in which the photoresist layer is artificially not sufficiently exposed. Where a distance between these boundary regions is smaller than a photolithographically critical, least distance, the photoresist layer is exposed, at a first boundary region, with a third exposure radiation and at a second boundary region with a fourth exposure radiation phase-shifted by 180°. A trim mask provided for the process has a first translucent region and a second translucent region. The first light-transparent region and the second light-transparent region are fashioned such that the light passing through the first light-transparent region and the light passing through the second light-transparent region has a phase displacement of 180°.

Abstract: An alternating phase mask is described in which a propagation of a T phase conflict which occurs in the case of a T pattern structure is avoided by producing a phase jump at one of the 90° corners of the T pattern structure. First and second transparent area segments, which produce a mutual phase difference of 180°, are separated by a narrow slot running approximately at 45° toward the corner of the T pattern structure. The structure containing the transparent area segments, which are separated by the slot running at 45°, can also be provided at the other corner of the T structure providing a solution for each T conflict. The trimming mask for eliminating the dark line artificially produced by the 180° phase jump is a conventional mask and requires no additional coloration. Moreover, alignment errors are minimal on account of the small number of trimming openings.

Abstract: In order to eliminate phase conflicts in alternating phase masks, the layout is modified after the phase conflicts have been localized. During the modification, degenerate critical structures, which fall below a minimum width and require phase-shifting regions for their adequate imaging, are widened, so that the phase-shifting regions directly adjoining the degenerate critical structures disappear. Moreover, interaction regions between phase-shifting regions can be eliminated by trimming masks, intermediate phases or shifting associated critical structures.

Abstract: An alternating phase mask having a branched structure containing two opaque segments is described. Two transparent surface segments are disposed on both sides of the segments or the components thereof, respectively. The surface segments are provided with phases that are displaced by 180°±&Dgr; &agr;, whereby &Dgr; &agr; a is not more than 25°. The surface segments are separated by at least one transparent surface boundary segment whose phase is situated between the phases of the adjacent surface segments.

Abstract: A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network description as well as information about the instantiations. A raw data structure represents the logical configuration of the layout and associates each instantiation with one, and only one, polygon data structure. A modified data structure is produced to represent the layout, which associates a circuit network description with one, and only one, polygon data structure, wherein the geometrical differences between the instantiations of this circuit network description are taken into account by variants in the polygon data structure.

Abstract: A method is used to check the direct convertibility of integrated semiconductor circuits into alternating phase masks. This is done by explicitly localizing the phase conflicts occurring in the corresponding layout while solely using the technological requirements made of the design. The set of phase conflicts determined with the aid of this formalism is complete and minimal and thus proves to be an optimum starting point for methods for handling conflicts of this type.

Abstract: A method for eliminating phase conflicts that occur in the layout of a phase mask in a localized and automated manner. The method includes a first step in which a set of phase conflicts is completely determined exclusively by using the technical requirements of the design. The first step is an optimum starting point for the following second step for automatically handling and eliminating such conflicts.