Abstract: The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.

Abstract: A baseband unit for a radio communication system based on time division multiple access includes a data processing unit configured to generate a configuration macro. The configuration macro includes information about a temporal position of a particular time slot within a time frame, wherein the particular time slot has a time duration corresponding to the total time duration of an integer number of consecutive data symbols.

Abstract: The invention is related to a data frame, particularly to a data frame configured to be received and processed by an RF-transceiver and a data frame structure. The invention is also related to a method for controlling an RF-transceiver.

Abstract: A description is given of a radio frequency module comprising an interface unit configured to receive macros having a first format from an input of the radio frequency module, a microprocessor coupled to the interface unit and operable to concert the macros having the first format to macros having a second format, a first memory coupled to the microprocessor and operable to store macros having the second format provided by the microprocessor and a first finite state machine implemented in hardware and configured to process macros having the second format accessed from the first memory.

Abstract: The present invention refers to an RF-transceiver and to a communication system. The invention is also related to a method for transmitting and processing control packets, particularly control packets transmitted by a baseband device to an RF-transceiver.

Abstract: A loop filter includes an input terminal, an output terminal, and a control terminal for a selection signal. At least one low pass filter is disposed between that input terminal and that output terminal. The loop filter is adapted to select a configuration out of a first configuration and at least one second configuration in response to the selection signal. In the first configuration, the loop filter comprises a non-integrating transfer characteristic in operation. In the second configuration, the loop filter comprises an integrating signal transfer characteristic in operation.

Abstract: A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.

Abstract: A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

Abstract: A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.

Abstract: A digital phase locked loop includes a digital phase detector, a downstream digital filter and an oscillator. In addition, a frequency divider resides in a feedback path and has an actuating input for setting a divider ratio, the input of which is connected to the oscillator and the phase detector. The phase locked loop comprises a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word to the actuating input of the frequency divider. The data word is configured such that the sigma-delta modulator generates jitter in the frequency setting word, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time.

Abstract: A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

Abstract: A radio-frequency IC (3) for a mobile radio transmitter (1) has an analogue/digital converter unit (5) for digitizing baseband signals (AB), a recovery unit (6, 7, 8, 9, 10) for recovering determined data information (Rot, TxSymbPhase) on which the baseband signals (AB) are based, a digital/analogue converter unit (11) and a frequency converter unit for producing transmitted signals on the basis of the signals produced by the digital/analogue converter unit (11).

Abstract: A frequency-dividing circuit arrangement is disclosed that includes a divider chain having a plurality of frequency divider stages. The frequency dividers can be changed over between the division ratios 2 and 3. At least that frequency divider that is arranged on the output side of the divider chain has an additional through-switching input that makes it possible to switch through the input signal to the output of the divider stage without influencing the delay-time effects of the divider stage. The advantages of a cascaded 2/3 divider chain, such as a high cut-off frequency, a simple design and the ability to arbitrarily expand, are thus achieved without accepting a lower limit of the range of possible division values.

Abstract: A transmitter includes a transformer that is configured to transform a baseband signal into an amplitude information signal and a phase information signal. The transmitter includes a ramping control unit configured to generate a power control signal. The transmitter includes a mixer that is configured to combine the amplitude information signal with the power control signal and produce a second amplitude information signal. The transmitter includes a modulator that is configured to modulate the second amplitude information signal on the phase information signal and produce an output signal.

Abstract: A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

Abstract: A frequency-dividing circuit arrangement is disclosed that includes a divider chain having a plurality of frequency divider stages. The frequency dividers can be changed over between the division ratios 2 and 3. At least that frequency divider that is arranged on the output side of the divider chain has an additional through-switching input that makes it possible to switch through the input signal to the output of the divider stage without influencing the delay-time effects of the divider stage. The advantages of a cascaded 2/3 divider chain, such as a high cut-off frequency, a simple design and the ability to arbitrarily expand, are thus achieved without accepting a lower limit of the range of possible division values.

Abstract: The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.

Abstract: A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.