Patents by Inventor Burkhard Steinmacher-Burow

Burkhard Steinmacher-Burow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • COORDINATION OF CACHE MEMORY OPERATIONS
    Publication number: 20190303295
    Abstract: The invention relates to a method for coordinating an execution of an instruction sequence by a processor device of a coherent shared memory system. An instruction is executed and causes the processor device to fill a copy of a memory line to a processor cache memory. The memory line is flagged by the processor device upon detection of first flag information which indicates that propagation of memory coherence across the shared memory system in respect of the memory line is unconfirmed. The memory line is unflagged by the processor device upon detection of second flag information which indicates that the propagation of memory coherence in respect of the memory line is confirmed. Upon execution of a memory barrier instruction, a completion of execution of the memory barrier instruction is prevented while the memory line is flagged.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventor: BURKHARD STEINMACHER-BUROW
  • CACHE LINE STATES IDENTIFYING MEMORY CACHE
    Publication number: 20190251029
    Abstract: A cache memory control device for controlling a first cache memory of a multi-cache memory system that includes logic circuitry operable for storing state information assigned to an invalid copy of a cache line stored in the first cache memory, where the state information includes a cache memory identifier identifying an individual second cache memory of the multi-cache memory system that is likely to contain a valid copy of the cache line.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Inventor: BURKHARD STEINMACHER-BUROW
  • REDUCED NUMBER OF COUNTERS FOR RELIABLE MESSAGING
    Publication number: 20190199653
    Abstract: A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Inventors: Sameer Kumar, Philip Heidelberger, Dong Chen, Yutaka Sugawara, Robert M. Senger, Burkhard Steinmacher-Burow
  • MEMORY BARRIERS IN A COHERENCE DIRECTORY
    Publication number: 20190179754
    Abstract: A method for issuing memory barrier instructions includes creating a transient table including records corresponding to one or more participant caches in a system, receiving a command for an address corresponding to one of the participant caches, determining whether one or more outstanding requests exist that must be executed before a barrier command is executed with respect to the participant cache, responsive to determining an outstanding request exists that must be executed before a barrier command is executed, incrementing a counter to reflect an instance in which an address with one or more outstanding requests was accessed, detecting the execution of the one or more outstanding requests, responsive to detecting the execution of the one or more outstanding requests, decrementing the counter, determining whether the counter has a value of zero, and responsive to determining the counter has a value of zero, issuing a memory barrier operation.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventor: Burkhard Steinmacher-Burow
  • NON-BLOCKING DIRECTORY-BASED CACHE COHERENCE
    Publication number: 20190179753
    Abstract: A computer implemented method for managing cache requests includes creating a transient table including records corresponding to one or more participant caches in a system, receiving a new request with respect to an address, wherein the request includes one or more controller actions to be executed, and wherein the request corresponds to one of the one or more participant caches in the system, determining whether an entry exists in the directory table corresponding to the address indicated by the received request, determining whether an entry exists in the transient table for the address indicated by the received request, processing the transient entry indicated by the index in the directory entry to provide a current state of the address indicated by the received request, and appropriating requested controller actions according to the directory table entry, the transient entry, and the received request.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Inventor: Burkhard Steinmacher-Burow
  • Memory access architecture with coherence
    Patent number: 10255184
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the computer system. One or more of the processor chips is communicatively coupled to at least one memory module which is assigned to the processor chip. One or more of the processor chips includes a cache and is communicatively coupled to one or more of the memory buffer chips via a memory-buffer-chip-specific bidirectional point-to-point communication connection. At least one of the memory buffer chips includes a coherence directory and is configured for being exclusively in charge for implementing directory-based coherence over the caches of the processor chips for at least one pre-defined address-based subset of memory lines stored in at least one of the memory modules assigned to a processor chip.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • MESSAGE ROUTING IN A MAIN MEMORY ARRANGEMENT
    Publication number: 20190065419
    Abstract: A memory hub device can be used to electrically interconnect a set of memory devices to a main memory arrangement. The memory hub device can include a set of ports for connecting memory devices to the memory hub device. The memory hub device can also include a coherence protocol processing circuit configured to process messages received from the memory devices through the ports and through a switch fabric coupled to the ports and to the coherence protocol processing circuit. The switch fabric can be configured to selectively forward messages received from memory devices through the ports to the coherence protocol processing circuit, or to another port used to transmit the message to the another memory device. The coherence protocol processing circuit can be used to process the messages.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 28, 2019
    Inventor: Burkhard Steinmacher-Burow
  • MESSAGE ROUTING IN A MAIN MEMORY ARRANGEMENT
    Publication number: 20190065418
    Abstract: A memory hub device can be used to electrically interconnect a set of memory devices to a main memory arrangement. The memory hub device can include a set of ports for connecting memory devices to the memory hub device. The memory hub device can also include a coherence protocol processing circuit configured to process messages received from the memory devices through the ports and through a switch fabric coupled to the ports and to the coherence protocol processing circuit. The switch fabric can be configured to selectively forward messages received from memory devices through the ports to the coherence protocol processing circuit, or to another port used to transmit the message to the another memory device. The coherence protocol processing circuit can be used to process the messages.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventor: Burkhard Steinmacher-Burow
  • Uniform memory access architecture
    Patent number: 10198373
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips and a methodology for operating the computer system. The memory buffer chips may be communicatively coupled to at least one memory module which can be configured for storing memory lines and assigned to the memory buffer chip. The processor chips can include a cache configured for caching memory lines. The processor chips may be communicatively coupled to the memory buffer chips via a memory-buffer-chip-specific bidirectional serial point-to-point communication connection. The processor chips can be configured for transferring memory lines between the cache of the processor chip and the memory modules via the respective memory-buffer-chip-specific bidirectional serial point-to-point communication connection.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Address layout over physical memory
    Patent number: 10169261
    Abstract: An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can include multiple memory devices, each including at least one memory portion. Each of the memory portions can be contiguous and have a uniform size. The memory line can be stored within one of the memory portions. The ATD can include a data table structure. Consecutive rows of the data table structure can be configured such that each of the rows uniquely identifies one of the memory portions. The ATD can also include an index calculation unit configured to calculate a row index. The row index can be used to identify the row of the data table structure that identifies the memory portion that includes the storage location of the memory line.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Remote processing and memory utilization
    Patent number: 10152450
    Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Address layout over physical memory
    Patent number: 10114772
    Abstract: An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can include multiple memory devices, each including at least one memory portion. Each of the memory portions can be contiguous and have a uniform size. The memory line can be stored within one of the memory portions. The ATD can include a data table structure. Consecutive rows of the data table structure can be configured such that each of the rows uniquely identifies one of the memory portions. The ATD can also include an index calculation unit configured to calculate a row index. The row index can be used to identify the row of the data table structure that identifies the memory portion that includes the storage location of the memory line.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • COALESCING MESSAGES USING A NETWORK INTERFACE CONTROLLER
    Publication number: 20180212902
    Abstract: An injection descriptor corresponding to a destination node may be stored in memory. A network interface controller (NIC) may determine that one or more messages added to the injection descriptor are to be transmitted to the destination node. The NIC may then lock the injection descriptor so that no additional message can be added to the injection descriptor, and the NIC may load the one or more messages. The NIC may then generate a network packet that includes the one or more messages, and the NIC may transmit the network packet to the destination node.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Inventor: Burkhard Steinmacher-Burow
  • Coalescing messages using a network interface controller
    Patent number: 10009296
    Abstract: An injection descriptor corresponding to a destination node may be stored in memory. A network interface controller (NIC) may determine that one or more messages added to the injection descriptor are to be transmitted to the destination node. The NIC may then lock the injection descriptor so that no additional message can be added to the injection descriptor, and the NIC may load the one or more messages. The NIC may then generate a network packet that includes the one or more messages, and the NIC may transmit the network packet to the destination node.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • UNIFORM MEMORY ACCESS ARCHITECTURE
    Publication number: 20180150419
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips and a methodology for operating the computer system. The memory buffer chips may be communicatively coupled to at least one memory module which can be configured for storing memory lines and assigned to the memory buffer chip. The processor chips can include a cache configured for caching memory lines. The processor chips may be communicatively coupled to the memory buffer chips via a memory-buffer-chip-specific bidirectional serial point-to-point communication connection. The processor chips can be configured for transferring memory lines between the cache of the processor chip and the memory modules via the respective memory-buffer-chip-specific bidirectional serial point-to-point communication connection.
    Type: Application
    Filed: February 15, 2018
    Publication date: May 31, 2018
    Inventor: Burkhard Steinmacher-Burow
  • UNIFORM MEMORY ACCESS ARCHITECTURE
    Publication number: 20180150418
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips and a methodology for operating the computer system. The memory buffer chips may be communicatively coupled to at least one memory module which can be configured for storing memory lines and assigned to the memory buffer chip. The processor chips can include a cache configured for caching memory lines. The processor chips may be communicatively coupled to the memory buffer chips via a memory-buffer-chip-specific bidirectional serial point-to-point communication connection. The processor chips can be configured for transferring memory lines between the cache of the processor chip and the memory modules via the respective memory-buffer-chip-specific bidirectional serial point-to-point communication connection.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventor: Burkhard Steinmacher-Burow
  • MEMORY ACCESS ARCHITECTURE WITH COHERENCE
    Publication number: 20180143906
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the computer system. One or more of the processor chips is communicatively coupled to at least one memory module which is assigned to the processor chip. One or more of the processor chips includes a cache and is communicatively coupled to one or more of the memory buffer chips via a memory-buffer-chip-specific bidirectional point-to-point communication connection. At least one of the memory buffer chips includes a coherence directory and is configured for being exclusively in charge for implementing directory-based coherence over the caches of the processor chips for at least one pre-defined address-based subset of memory lines stored in at least one of the memory modules assigned to a processor chip.
    Type: Application
    Filed: February 6, 2018
    Publication date: May 24, 2018
    Inventor: Burkhard Steinmacher-Burow
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • MEMORY ACCESS ARCHITECTURE WITH COHERENCE
    Publication number: 20180129606
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the computer system. One or more of the processor chips is communicatively coupled to at least one memory module which is assigned to the processor chip. One or more of the processor chips includes a cache and is communicatively coupled to one or more of the memory buffer chips via a memory-buffer-chip-specific bidirectional point-to-point communication connection. At least one of the memory buffer chips includes a coherence directory and is configured for being exclusively in charge for implementing directory-based coherence over the caches of the processor chips for at least one pre-defined address-based subset of memory lines stored in at least one of the memory modules assigned to a processor chip.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 10, 2018
    Inventor: Burkhard Steinmacher-Burow
  • Data processing system with main and balcony boards
    Patent number: 9953004
    Abstract: A data processing system with a main board and balcony boards. The data processing system includes a mainboard, at least one processor module, and at least one memory module. The system has at least one balcony board carrying at least one of the processor modules and at least one of the memory modules. The processor module has a first pin area for connecting to the balcony board and a second pin area for connecting to the mainboard, such that the balcony board is attached to the mainboard in a fixed position. The balcony board has an opening through which the processor module is plugged in a socket attached to the mainboard. The mainboard has an opening through which the processor module is plugged in a socket attached to the balcony board. A mainboard and a balcony board for a data processing system is also provided.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Burkhard Steinmacher-Burow