Abstract: Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

Abstract: Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

Abstract: Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

Abstract: Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

Abstract: A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

Abstract: A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.

Abstract: A data center for executing a data processing application includes processing units, sub-units or servers. Each of the processing units, sub-units or servers can execute a part or all of the data processing application. The processing units, sub-units or servers are electrical disjoint with respect to data communications, but can communicate with each other over free space optical links.

Abstract: Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage.

Abstract: Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Abstract: A data center for executing a data processing application includes processing units, sub-units or servers. Each of the processing units, sub-units or servers can execute a part or all of the data processing application. The processing units, sub-units or servers are electrical disjoint with respect to data communications, but can communicate with each other over free space optical links.

Abstract: A data center for executing a data processing application includes processing units, sub-units or servers. Each of the processing units, sub-units or servers can execute a part or all of the data processing application. The processing units, sub-units or servers are electrical disjoint with respect to data communications, but can communicate with each other over free space optical links.

Abstract: The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage.

Abstract: An exemplary method includes writing data to locations in non-volatile solid-state memory and deciding whether to move data written to one location in the memory to another location in the memory based on generation of the data and wear of the other location. Such a method may be used for non-volatile random access memory (NVRAM). Various other methods, devices, systems, etc., are also disclosed.

Abstract: An exemplary method includes hosting a service at a data center, the service relying on at least one software component developed according to a programming model and the data center comprising a corresponding programming model abstraction layer that abstracts resources of the data center; receiving a request for the service; and in response to the request, assigning at least some of the resources of the data center to the service to allow for fulfilling the request wherein the programming model abstraction layer performs the assigning based in part on reference to a resource class in the at least one software component, the resource class modifiable to account for changes in one or more resources of the data center. Various other devices, systems and methods are also described.

Abstract: This patent application pertains to urgency-based resource management in computing scenarios. One implementation can identify processes competing for resources on a system. The implementation can evaluate an urgency of individual competing processes. The implementation can also objectively allocate the resources among the competing processes in a manner that reduces a total of the urgencies of the competing processes.

Abstract: An exemplary method for performing work in a data center includes receiving a request for resources in a data center, solving a linear programming formulation that accounts for the request and at least some of the resources in the data center and performing work the request based at least in part on the solving of the linear programming formulation. Such a method can include a linear programming formulation that accounts for multi-core chips and DRAM systems. Various other method, devices, systems, etc., are also disclosed.