Patents by Inventor Burton Jesse CARPENTER
Burton Jesse CARPENTER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11967507Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: GrantFiled: December 6, 2021Date of Patent: April 23, 2024Assignee: NXP USA, INC.Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
-
Publication number: 20230197645Abstract: Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Zhiwei Gong, LI Li, Lu Li, Lakshminarayan Viswanathan, Fernando A. Santos, Burton Jesse Carpenter
-
Publication number: 20230085441Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package leadframe having a first die pad and a second die pad separated from the first die pad. A first semiconductor die is attached to the first die pad of the package leadframe. A second semiconductor die is attached to the second die pad of the package leadframe. A communication device is attached over the second semiconductor die. The communication device is configured to communicate wirelessly with the second semiconductor die.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Jerry Rudiak, Burton Jesse Carpenter, Fred T. Brauchler
-
Patent number: 11502068Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.Type: GrantFiled: March 3, 2021Date of Patent: November 15, 2022Assignee: NXP USA, INC.Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Patent number: 11462494Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device package includes a package substrate having a first inductive coil. A first semiconductor die is attached to a first major surface of the package substrate. The first semiconductor die includes a second inductive coil substantially aligned with the first inductive coil. A second semiconductor die is attached to the first major surface of the package substrate. A wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.Type: GrantFiled: September 28, 2020Date of Patent: October 4, 2022Assignee: NXP USA, INC.Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Publication number: 20220285330Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.Type: ApplicationFiled: March 3, 2021Publication date: September 8, 2022Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Publication number: 20220102292Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device package includes a package substrate having a first inductive coil. A first semiconductor die is attached to a first major surface of the package substrate. The first semiconductor die includes a second inductive coil substantially aligned with the first inductive coil. A second semiconductor die is attached to the first major surface of the package substrate. A wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Publication number: 20220093416Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
-
Patent number: 11222790Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: GrantFiled: April 29, 2020Date of Patent: January 11, 2022Assignee: NXP USA, INC.Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
-
Patent number: 11164826Abstract: A packaged integrated circuit (IC) device includes a first IC die, a first layer of adhesive on a first major surface of the first IC die, and an isolation layer over the first layer of adhesive. The isolation layer has a first major surface and a second major surface, and the second major surface of the isolation layer is between the first layer of adhesive and the first major surface. The packaged IC device also includes a first inductor coil on the first major surface of the isolation layer, a second layer of adhesive on the isolation layer, and a second IC die on the second layer of adhesive.Type: GrantFiled: August 30, 2019Date of Patent: November 2, 2021Assignee: NXP USA, Inc.Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Publication number: 20210202267Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.Type: ApplicationFiled: April 29, 2020Publication date: July 1, 2021Inventors: Richard Te Gan, Rushik Prabhudas Tank, Zhiwei Gong, Burton Jesse Carpenter, Jinmei Liu
-
Publication number: 20210066217Abstract: A packaged integrated circuit (IC) device includes a first IC die, a first layer of adhesive on a first major surface of the first IC die, and an isolation layer over the first layer of adhesive. The isolation layer has a first major surface and a second major surface, and the second major surface of the isolation layer is between the first layer of adhesive and the first major surface. The packaged IC device also includes a first inductor coil on the first major surface of the isolation layer, a second layer of adhesive on the isolation layer, and a second IC die on the second layer of adhesive.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Inventors: Burton Jesse Carpenter, Fred T. Brauchler
-
Patent number: 10734327Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.Type: GrantFiled: January 3, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Mariano Layson Ching, Jr., Burton Jesse Carpenter, Jinmei Liu, Yit Meng Lee, Allen Marfil Descartin
-
Patent number: 10734311Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.Type: GrantFiled: January 7, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Mariano Layson Ching, Jr., Burton Jesse Carpenter, Lidong Zhang, Kendall Dewayne Phillips, Quan Chen, Meng Kong Lye
-
Patent number: 10734312Abstract: A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.Type: GrantFiled: July 18, 2018Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Burton Jesse Carpenter, Kim Roger Gauen
-
Publication number: 20200203262Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.Type: ApplicationFiled: January 7, 2019Publication date: June 25, 2020Inventors: Mariano Layson CHING, JR., Burton Jesse CARPENTER, Lidong ZHANG, Kendall Dewayne PHILLIPS, Quan CHEN, Meng Kong LYE
-
Publication number: 20200203289Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.Type: ApplicationFiled: January 3, 2019Publication date: June 25, 2020Inventors: Mariano Layson CHING, JR., Burton Jesse Carpenter, Jinmei Liu, Yit Meng Lee, Allen Marfil Descartin
-
Publication number: 20200027823Abstract: A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.Type: ApplicationFiled: July 18, 2018Publication date: January 23, 2020Inventors: BURTON JESSE CARPENTER, Kim Roger Gauen
-
Patent number: 10446476Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.Type: GrantFiled: March 19, 2018Date of Patent: October 15, 2019Assignee: NXP USA, Inc.Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
-
Patent number: 10249557Abstract: A packaged lead frame includes a encapsulant having a first minor side, a second minor side opposite the first minor side, a third minor side, and a fourth minor side opposite the third minor side, and a plurality of leads along the third minor side between the first minor side and a center plane between the first and second minor side. The plurality of leads extend outwardly from the encapsulant at a first plane. Each of the plurality of leads includes a corresponding jog external to the encapsulant which jogs away from the center plane, wherein the corresponding jog of each lead from a first lead of the plurality of leads closest to the center plane to a last lead of the first plurality of leads closest to the first minor side jogs incrementally further away the center plane.Type: GrantFiled: May 23, 2017Date of Patent: April 2, 2019Assignee: NXP USA, Inc.Inventors: Leo M. Higgins, III, Burton Jesse Carpenter