Patents by Inventor Bushnaq SANAD

Bushnaq SANAD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS
    Publication number: 20230317177
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: Kioxia Corporation
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • Memory device which generates operation voltages in parallel with reception of an address
    Patent number: 11705210
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS
    Publication number: 20220130469
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • Memory device which generates operation voltages in parallel with reception of an address
    Patent number: 11257551
    Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • MEMORY DEVICE WHICH GENERATES OPERATION VOLTAGES IN PARALLEL WITH RECEPTION OF AN ADDRESS
    Publication number: 20210158879
    Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • Memory device which generates operation voltages in parallel with reception of an address
    Patent number: 10957404
    Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Semiconductor memory device
    Patent number: 10896735
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Bushnaq Sanad, Noriyasu Kumazaki, Yuzuru Shibazaki
  • MEMORY DEVICE
    Publication number: 20200202958
    Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.
    Type: Application
    Filed: September 11, 2019
    Publication date: June 25, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20200194077
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.
    Type: Application
    Filed: September 9, 2019
    Publication date: June 18, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Bushnaq SANAD, Noriyasu KUMAZAKI, Yuzuru SHIBAZAKI