Abstract: An electrically programmable memory cell of a type having a source, a drain, a floating gate and a control gate formed over a face of a semiconductor substrate in which a ring region of material doped similarly to the substrate encloses the source, drain and gates and extends to a surface of the substrate around its length. Drain and source coupling regions of material doped oppositely to the substrate contact the drain and source, respectively, within the ring and extend under the ring to the substrate surface outside of the ring defining drain and source contact regions, respectively. A contact outside the ring to the control gate is provided by a gate coupling region also extending under the ring to a substrate surface on either side thereof. An interconnect couples the floating gate to the gate coupling region. A non-light transmitting, electrically conducting shield extends over the cell contacting the ring region around its periphery at the substrate surface.