Patents by Inventor But-Chung Chiu

But-Chung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128231
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
  • Publication number: 20240104352
    Abstract: Provided are improved end-to-end self-supervised pre-training frameworks that leverage a combination of contrastive and masked modeling loss terms. In particular, the present disclosure provides framework that combines contrastive learning and masked modeling, where the former trains the model to discretize input data (e.g., continuous signals such as continuous speech signals) into a finite set of discriminative tokens, and the latter trains the model to learn contextualized representations via solving a masked prediction task consuming the discretized tokens. In contrast to certain existing masked modeling-based pre-training frameworks which rely on an iterative re-clustering and re-training process or other existing frameworks which concatenate two separately trained modules, the proposed framework can enable a model to be optimized in an end-to-end fashion by solving the two self-supervised tasks (the contrastive task and masked modeling) simultaneously.
    Type: Application
    Filed: July 28, 2022
    Publication date: March 28, 2024
    Inventors: Yu Zhang, Yu-An Chung, Wei Han, Chung-Cheng Chiu, Weikeng Qin, Ruoming Pang, Yonghui Wu
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240080024
    Abstract: A driving method for a multiple frequency coupling generator is provided. The method includes: in normal operations, interpreting an input digital control signal transmitted from a digital signal processor into an interpreted digital control signal; interpreting the interpreted digital control signal into a plurality of magnetic coupling signals by a magnetic coupling switch circuit; performing signal recovery and differential delay on the magnetic coupling signals by an interlocking circuit for reducing time difference and signal loss of the magnetic coupling signals; and when the interlocking circuit determines that the magnetic coupling signals have substantially no time difference and no signal loss, transforming the magnetic coupling signals into a first driving signal and a second driving signal by a switch circuit, a driver circuit and an output pad group to drive a backend driving loop.
    Type: Application
    Filed: March 30, 2023
    Publication date: March 7, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Chung CHIU, Hung-Yi TENG, Chi-Chung LIAO, Shou-Chung HSIEH, Ke-Horng CHEN, Yan-Fu JHOU
  • Patent number: 11908746
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
  • Publication number: 20240014293
    Abstract: Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chih-Han Li, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11842929
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chen-Yui Yang, Ke-Chia Tseng, Hsien-Chung Huang, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20230395677
    Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Chung CHIU, Ke-Chia TSENG, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
  • Publication number: 20230386778
    Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Ching-Heng YEN, Jen-Chung CHIU, Tai-Kun KAO, Lu-Hsun LIN, Tsung-Min LIN
  • Patent number: 11830700
    Abstract: The current disclosure is directed to a repellent electrode used in a source arc chamber of an ion implanter. The repellent electrode includes a shaft and a repellent body having a repellent surface. The repellent surface has a surface shape that substantially fits the shape of the inner chamber space of the source arc chamber where the repellent body is positioned. A gap between the edge of the repellent body and the inner sidewall of the source arc chamber is minimized to a threshold level that is maintained to avoid a short between the conductive repellent body and the conductive inner sidewall of the source arc chamber.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Heng Yen, Jen-Chung Chiu, Tai-Kun Kao, Lu-Hsun Lin, Tsung-Min Lin
  • Patent number: 11808949
    Abstract: The present invention provides a lens driving device, a camera and an electronic apparatus with a small size and an excellent effect in hand vibration correction. The lens driving device includes a case having an accommodation space, in which a lens module is provided. The lens module includes a lens, a lens holder receiving the lens, a support frame for freely rotating the lens holder in a direction orthogonal to an optical axis direction, support members, an electromagnetic driving device, and a base for fixing a circuit board; the electromagnetic driving device is arranged on the lens holder and the base for fixing the circuit board, and is provided adjacent to a level of a center of gravity of the lens module; and the lens module have different movement axes in a plane and is rotatable freely relative to the base for fixing the circuit board.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 7, 2023
    Assignee: Changzhou Raytech Optronics Co., Ltd.
    Inventors: Ching-Chung Chiu, Kazuo Shikama
  • Publication number: 20230343491
    Abstract: An ignition resistor comprises a substrate, two antistatic layers, an ignition structure and a protective layer. The ignition structure is attached to the upper surface of the substrate through an adhesive layer, wherein the ignition structure includes two electrode portions and an ignition portion, the two electrode portions are respectively connected to two opposite ends of the ignition portion. The two antistatic layers are respectively disposed on the opposite sides of the ignition portion and the upper surface of the substrate between the two electrode portions, and the protective layer covers the ignition portion.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 26, 2023
    Inventors: WIE-LIN CHIANG, CHENG-CHUNG CHIU, SHUN-HO KUO, CHI-YU LU
  • Publication number: 20230326146
    Abstract: An augmented reality implementing method applied to a server, which includes a plurality of augmented reality objects and a plurality of setting records corresponding to the augmented reality objects respectively is provided. Firstly, the server receives an augmented reality request from a mobile device, where the augmented reality request is related to a target device. Then, the server is communicated with the target device to access current information. Then, the server determines the current information corresponds to which one of the setting records, and selects one of the augmented reality objects based on the determined setting record as a virtual object provided to the mobile device.
    Type: Application
    Filed: October 4, 2022
    Publication date: October 12, 2023
    Inventors: Kuo-Chung CHIU, Hsuan-Wu WEI, Yen-Ting LIU, Shang-Chih LIANG, Shih-Hua MA, Yi-Hsuan TSAI, Jun-Ting CHEN, Kuan-Ling CHEN
  • Publication number: 20230326990
    Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20230326635
    Abstract: A thin film resistor is provided, and a resistance layer of the thin film resistor is a patternized mesh. The mesh density of the mesh resistance layer increases from center to both ends of the film resistor. The temperature peak is shifted from the center to both ends of the film resistor. Therefore, the heat can be quickly dissipated via the electrodes.
    Type: Application
    Filed: April 5, 2023
    Publication date: October 12, 2023
    Inventors: ZHONG-YU CHEN, CHENG-CHUNG CHIU, SHUN-HO KUO, CHI-YU LU
  • Patent number: 11764801
    Abstract: A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 19, 2023
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shiau-Wen Kao, Ying-Chung Chiu
  • Publication number: 20230252552
    Abstract: An e-gifting method is provided. The method is performed by a computer device including a processing unit, and includes: receiving, by the processing unit, gift filtering information and receiver information from a giver terminal device; generating, by the processing unit, a candidate gift list according to the gift filtering information and the receiver information, where the candidate gift list includes a plurality of candidate gift items; generating, by the processing unit, a gifting list from the candidate gift items according to giver selecting information from the giver terminal device, where the gifting list includes a plurality of gifting gift items; confirming, by the processing unit, a selected gift item from the gifting gift items according to receiver selecting information from a receiver terminal device; and transmitting, by the processing unit, payment information corresponding to the selected gift item to the giver terminal device.
    Type: Application
    Filed: September 7, 2022
    Publication date: August 10, 2023
    Inventors: Kuo-Chung CHIU, Hsuan-Wu WEI, Yi-Hua HUANG, Chun-Hao LIAO
  • Patent number: 11715779
    Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yao Lin, Chih-Chung Chiu, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Patent number: 11693492
    Abstract: A mouse is provided. The mouse includes a casing, a circuit board, a micro switch base, and a micro switch. The casing includes a button. The circuit board is disposed in the casing. The micro switch base is disposed on the circuit board, and includes a plurality of first openings and a plurality of second openings. The micro switch is fixed on the micro switch base through at least one of the first openings, and electrically connected to the circuit board through the first openings or the second openings.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 4, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chi-Fan Chen, Yi-Chung Chiu, Chen-Hou Lo
  • Publication number: 20230186751
    Abstract: A system and method for deciphering signals and messages from a control unit, and mapping those signals to the associated sensors to create a map of the sensor status. The map of the sensor status is then used in conjunction with a dongle and software application to interface with the control unit, able to receive messages from the control unit to monitor the status of the sensors, and to send messages to the control unit to manipulate the sensors. The system and method can further be used to interface with the electronic control unit of a vehicle to detect unattended access of the vehicle and ensure no passengers are left abandoned in the vehicle, such as by sending alerts to a mobile device of the user, triggering alarms in the vehicle, or sending alerts to emergency services.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 15, 2023
    Inventors: Tracey Carl Roberts, Kuan-Chung Chiu