Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.

Abstract: Aspects of the present disclosure involve an apparatus including a port interface coupled with a data bus to receive memory transaction commands, and a command queue coupled with the port interface. Additional aspects include methods of operating such an apparatus, and electronic design automation (EDA) devices to generate design files associated with such an apparatus. The command queue includes a plurality of memory entries to store memory transaction commands, a placement logic module to combine a received memory transaction command with a memory transaction command previously stored in one of the plurality of memory entries of the command queue, and a selection logic module to determine an order to transmit memory transaction commands stored in the plurality of memory entries and transmit the stored memory transaction commands according to the determined order to a memory interface.

Abstract: Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an advanced low power mode that can further reduce power consumption in different modes at each suitable idle time based on different command types.

Abstract: Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.