Patents by Inventor Bwo-Ning Chen
Bwo-Ning Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949016Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.Type: GrantFiled: May 13, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
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Patent number: 11935954Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: GrantFiled: July 30, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Chien-Tai Chan
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Publication number: 20240079465Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature electrically coupled to the vertical stack of channel members, a silicide layer formed on more than one side of the source/drain feature, and a source/drain contact electrically coupled to the source/drain feature via the silicide layer.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Chun-Fai Cheng, Bwo-Ning Chen, Chang-Miao Liu
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Patent number: 11916105Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: GrantFiled: March 26, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
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Publication number: 20230387199Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
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Publication number: 20230378365Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
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Patent number: 11728405Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.Type: GrantFiled: March 16, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Shih-Hao Lin
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Patent number: 11688647Abstract: A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.Type: GrantFiled: July 28, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xu-Sheng Wu, Chang-Miao Liu
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Publication number: 20230200264Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.Type: ApplicationFiled: February 22, 2023Publication date: June 22, 2023Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
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Publication number: 20230060786Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first portion of an oxide layer around the dummy contact structure, performing a second etching process to at least partially remove the first portion of oxide layer, forming a spacer layer around the dummy contact structure, performing a second deposition process to form a second portion of the oxide layer around the spacer layer, removing the spacer layer and the dummy contract structure to leave an opening, and filling the opening with a conductive material to form a conductive plug.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Bwo-Ning Chen, Xusheng Wu, Yin-Pin Wang, Yuh-Sheng Jean, Chang-Miao Liu
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Patent number: 11594680Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.Type: GrantFiled: September 1, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
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Publication number: 20230035791Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bwo-Ning CHEN, Xusheng WU, Chang-Miao LIU, Chien-Tai CHAN
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Publication number: 20220384618Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
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Publication number: 20220367677Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Bwo-Ning CHEN, Xusheng WU, Chang-Miao LIU, Shih-Hao LIN
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Publication number: 20220367726Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
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Patent number: 11482610Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.Type: GrantFiled: July 17, 2020Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
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Publication number: 20220310783Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
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Publication number: 20210399221Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.Type: ApplicationFiled: September 1, 2021Publication date: December 23, 2021Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
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Publication number: 20210358814Abstract: A semiconductor device includes an N-type fin-like field effect, a P-type fin-like field effect transistor, a shallow trench isolation (STI) structure, a first interlayer dielectric (ILD) layer, and a second ILD layer. The N-type fin-like field effect transistor includes a first semiconductor fin, a gate structure across the first semiconductor fin, and a first source/drain feature in contact with the first semiconductor fin. The P-type fin-like field effect transistor includes a second semiconductor fin, the gate structure across the second semiconductor fin, and a second source/drain feature in contact with the second semiconductor fin. The structure surrounds the first and second semiconductor fins. The first interlayer dielectric (ILD) layer covers the first source/drain feature. The second ILD layer covers the second source/drain feature, wherein a porosity of the second ILD layer is greater than a porosity of the first ILD layer.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning CHEN, Xu-Sheng WU, Chang-Miao LIU
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Publication number: 20210313514Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen