Abstract: A data sensing control circuit according to the present invention is provided in a semiconductor memory device with a burst access mode. The data sensing control circuit generates sensing control signals for data sensing operation by use of a transition information of an address bit signal synchronized with a read enable clock signal and used for a bank selection. According to such a data sensing control scheme, no sensing of each sensing period is performed when the read enable clock signal transitions. Therefore, a power noise (or input/output noise) issued at data-out does not affect the data sensing operation of the semiconductor memory device having the burst access mode.

Abstract: A memory comprising a plurality of memory blocks having a plurality of memory cells and wordlines, each of the memory blocks having selection lines by which the memory blocks are selected. The selection lines are shared between neighboring blocks. In addition, a wordline switching circuit is coupled between conductors carrying wordline drive signals and the wordlines, and a block selection line circuit is coupled between conductors carrying the block selection lines signals and the block selection lines. A selection control circuit supplies selection control signals to the wordline switching circuit and the block selection line switching circuit. The selection control circuit generates the selection control signals in response to address informing signals. The selection lines are coupled to discharge circuits, which pull down voltage levels of selection lines that are not selected.

Abstract: An integrated circuit multi-bit memory device incorporating an error check and correction (ECC) technique is provided. In the error correction, two or more groups of parity bits corresponding to a data word of the multi-bit memory device are programmed therein. The groups are classified by the number of bits per cell. Error bits in a memory data word are checked sequentially by the group, and the checked error bits are also corrected sequentially by the group, thereby preventing the device failure due to two or more errors in a data word of the multi-bit memory device.

Abstract: The disclosed is a read only memory having a plurality of memory blocks each associated with main bit lines and sub-bit lines, and a plurality of memory cells for storing information, and sense amplifiers for reading the information stored in the memory cells through the main bit lines. The memory also has a block selection part disposed between the blocks and having a plurality of block selection transistors connecting the main bit lines to the sub-bit lines. The sub-bit lines elongate to at least an adjacent block and alternatively connected to the main bit lines through the block selection part.

Abstract: A plurality of memory cell referenced regulators is connected to an output terminal that is configured to connect to a plurality of memory cells of a multi-level memory device. A respective one of the memory cell referenced regulators includes a respective dummy memory cell having a respective predetermined threshold voltage. The plurality of memory cell referenced regulators are responsive to a select signal such that a selected one of the memory cell referenced regulators varies a current at the output terminal to maintain the output terminal at a voltage proportional to the threshold voltage of the dummy memory cell of the selected memory cell referenced regulator. Each of the memory cell referenced regulators may comprise a variable current mirror having a controlled current path and an output current path including the output terminal.

Abstract: A read-only memory device having a NOR structure is provided. The memory device comprises a memory cell array having a plurality of memory cells, each memory cell storing data, a plurality of first bit lines coupled to the array, and a plurality of second bit lines coupled to the array. A first selection circuit are coupled to the plurality of first bit lines for selecting at least two adjacent first bit lines. A second selection circuit coupled to the plurality of second bit lines for selecting at least two adjacent second bit lines. A sense amplification circuit detect a cell state of a selected memory cell by biasing the selected first bit lines and one of the selected second bit lines with a same potential. The second selection circuit grounds another of the selected second bit lines. The first selection circuit grounds unselected first bit lines and wherein the second selection circuit grounds unselected second bit lines.

Abstract: A word line voltage generating apparatus is provided for a multi-level memory device including a plurality of memory cells, each of which has a programmable threshold voltage such that the memory cell produces a current in response to a word line voltage applied thereto.

Abstract: The disclosure is a read only memory having a memory cell array formed of a plurality of memory cells coupled to wordlines and bitlines, the bitlines being alternately connected to main bitlines and ground lines. The invented read only memory include an address transition detection signal source. It also includes a first delay circuit for receiving the address transition detection signal and for generating a first discharge signal for driving the ground lines. It also includes a second delay circuit for receiving the address transition detection signal and for generating a second discharge signal for driving the main bitlines. It also includes a first pulse circuit for receiving the first discharge signal and for generating a first precharge signal for driving the ground lines. Finally, it includes a second pulse circuit for receiving the second discharge signal and for generating a second precharge signal for driving the main bitlines.

Abstract: Disclosed is a semiconductor memory device and a method for reading data stored therein. The device comprises a cell array having a plurality of groups, sub-bit lines, word lines, main bit lines, each of the groups having memory cells connected in parallel between the sub bit lines, first NMOS transistors for selecting even-numbered groups of the groups, second NMOS transistors for selecting odd-numbered groups of the groups, a voltage generating circuit for generating a first voltage by dividing an externally applied power supply voltage, a row selecting circuit for selecting one of the word lines in response to an external row address signal; a column selecting circuit for selecting column of the cell array in response to an external column address signal, and a sense amplifier circuit for sensing the data of memory cell associated with the selected word line and the selected main bit line.

Abstract: Disclosed is a nonvolatile memory, compatible with a dynamic random access memory, including a memory array divided into a plurality of blocks, each of the blocks being divided into a plurality of sub-blocks, reading and writing row decoders for selecting rows of the memory array, and reading and writing gate drive circuits for selecting a plurality of drive lines which supply source voltages to the rows of the memory array, wherein the memory array employs a plurality of section decoders which are arranged between the sub-blocks, each of the section decoders being assigned to a half of the rows belong to the sub-block and connecting the drive lines to the rows.

Abstract: A semiconductor memory device includes a precharge circuit for precharging bit lines responsive to a first control signal during a bit line precharge period and a plurality of transistors each having a current path connected between the corresponding bit line and the precharge circuit. The memory device also includes a control terminal for receiving a second control signal, a data sensing circuit for sensing data states on the bit lines during a data sensing period, and a control circuit for generating the first and second control signals. The second control signal has a first and a second voltage levels during the bit line precharge period and the data sensing period, respectively. The first voltage level is different from the second voltage level. As a result, the corresponding sensing node between the transistors and the data sensing means is maintained to a preset voltage without transitorily dropping during a data sensing period.

Abstract: Disclosed is a nonvolatile memory having lockable cell array. The memory includes a lockable cell array formed of a plurality of lockable cell transistors and lockable word lines coupled to gates of the lockable cell transistors; and a lockable pass transistor array formed of a plurality of lockable pass transistors connecting the lockable word lines to a plurality of selection signals. The lockable word lines are coupled to boosting elements which are in response to capacitive coupling in a bulk during an unlock operation.

Abstract: A common source line control circuit for a semiconductor memory device includes a resistor connected in series with a transistor to reduce the voltage across the transistor, thereby preventing snap back breakdown. The resistor and transistor are connected in series with a second transistor which together form a current path between the bulk region of a memory cell array and a ground node for discharging the bulk region during an erase voltage recovery period. The resistor can be connected between the transistors or between one transistor and the bulk region. A second resistor can be connected in series with the other resistor and the two transistors. The resistance values of the resistors are larger than the channel resistances of the transistors.

Abstract: Methods of programming flash EEPROM integrated circuit memory devices containing an array of NAND cells therein include the steps of applying a preselected logic signal to a select transistor of a NAND memory cell to inhibit the likelihood of inadvertent programming thereof when adjacent cells are being programmed. According to one embodiment, a first logic signal having a first non-zero potential (V.sub.fp) is applied to a bit line BL of a first NAND memory cell in the array. Then, at commencement of a first time interval (TI), a second logic signal having a second potential which is greater than the first potential is applied to the gate (SSL) of the first select transistor ST1 to thereby turn-on the first select transistor "hard" and drive the potential of a source (S) thereof towards the potential of the bit line (i.e., V.sub.fp). Here, the first potential V.sub.fp is preferably selected to be higher than the power supply voltage VCC.