Patents by Inventor Byeong-Chan Choi
Byeong-Chan Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096557Abstract: A capacitor component includes a body having a first surface and a second surface opposing each other and including a multilayer structure in which a plurality of dielectric layers are stacked and first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween and exposed to the first surface and the second surface, respectively, first and second metal layers covering the first surface and the second surface and connected to the first and second internal electrodes, respectively, first and second ceramic layers covering the first and second metal layers, and first and second external electrodes covering the first and second ceramic layers and connected to the first and second metal layers to be electrically connected to the first and second internal electrodes, respectively.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Sung Hyun CHO, Byeong Chan KWON, Yong Jin YUN, Ki Pyo HONG, Jae Yeol CHOI
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Patent number: 11693564Abstract: An apparatus includes a storage area signal generation circuit configured to generate a storage area signal when performing an internal information storage operation and an external information storage operation; and an information storage circuit configured to receive internal failure information, stored in the apparatus, based on the storage area signal and store the received internal failure information as failure information in a set storage capacity, and store external failure information, applied from outside the apparatus, as the failure information in a variable storage capacity.Type: GrantFiled: May 25, 2021Date of Patent: July 4, 2023Assignee: SK hynix Inc.Inventor: Byeong Chan Choi
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Publication number: 20220229563Abstract: An apparatus includes a storage area signal generation circuit configured to generate a storage area signal when performing an internal information storage operation and an external information storage operation; and an information storage circuit configured to receive internal failure information, stored in the apparatus, based on the storage area signal and store the received internal failure information as failure information in a set storage capacity, and store external failure information, applied from outside the apparatus, as the failure information in a variable storage capacity.Type: ApplicationFiled: May 25, 2021Publication date: July 21, 2022Applicant: SK hynix Inc.Inventor: Byeong Chan CHOI
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Publication number: 20220001463Abstract: Provided are a hole machining apparatus for an optical film, comprising: a clamping part for fixing a plurality of optical films in stacked laminated state; and a machining part for performing a hole operation on a predetermined region of the plurality of optical films so as to sequentially pass through the optical films along the laminated direction in a state where the optical films are fixed to the clamping part, wherein upon the hole operation, the machining part comprises a drill part provided to perform a primary hole machining operation and a bite unit provided to perform a secondary hole operation in the primary hole operation region. Also provided is a hole machining method for an optical film, comprising clamping a plurality of laminated optical films at a predetermined pressure in the hole machining apparatus.Type: ApplicationFiled: October 21, 2019Publication date: January 6, 2022Inventors: Seong Yong WE, Sung Wook HWANG, Bum Seung LIM, Byeong Chan CHOI, Seul Ki PARK, Ye Jin MUN, Woo Yong SONG, Zi Shuo ZHANG
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Patent number: 11145351Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.Type: GrantFiled: August 3, 2020Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventors: Jung Ho Lim, Byeong Chan Choi
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Publication number: 20210142848Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.Type: ApplicationFiled: August 3, 2020Publication date: May 13, 2021Applicant: SK hynix Inc.Inventors: Jung Ho LIM, Byeong Chan CHOI
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Patent number: 9514849Abstract: A semiconductor memory device includes a first fuse set block including a fuse array for storing first repair information, and a control block configured to store second repair information in a first mode, and generate an output control signal when input addresses applied from an external source and the second repair information are the same, in a second mode, wherein the first fuse set block enables a first match signal for accessing a first redundancy memory cell when the stored first repair information and the input addresses are the same, and disables the first match signal in response to the output control signal.Type: GrantFiled: September 15, 2015Date of Patent: December 6, 2016Assignee: SK Hynix Inc.Inventors: Jung-Taek You, Byeong-Chan Choi
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Publication number: 20160300627Abstract: A semiconductor memory device includes a first fuse set block including a fuse array for storing first repair information, and a control block configured to store second repair information in a first mode, and generate an output control signal when input addresses applied from an external source and the second repair information are the same, in a second mode, wherein the first fuse set block enables a first match signal for accessing a first redundancy memory cell when the stored first repair information and the input addresses are the same, and disables the first match signal in response to the output control signal.Type: ApplicationFiled: September 15, 2015Publication date: October 13, 2016Inventors: Jung-Taek YOU, Byeong-Chan CHOI
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Publication number: 20150357051Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.Type: ApplicationFiled: August 19, 2015Publication date: December 10, 2015Inventors: Doo-Chan LEE, Byeong-Chan CHOI, One-Gyun NA
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Publication number: 20150357052Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.Type: ApplicationFiled: August 19, 2015Publication date: December 10, 2015Inventors: Doo-Chan LEE, Byeong-Chan CHOI, One-Gyun NA
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Patent number: 9142325Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.Type: GrantFiled: December 15, 2013Date of Patent: September 22, 2015Assignee: SK Hynix Inc.Inventors: Doo-Chan Lee, Byeong-Chan Choi, One-Gyun Na
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Publication number: 20150098286Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.Type: ApplicationFiled: December 15, 2013Publication date: April 9, 2015Applicant: SK hynix Inc.Inventors: Doo-Chan LEE, Byeong-Chan CHOI, One-Gyun NA
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Patent number: 8891325Abstract: A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.Type: GrantFiled: September 3, 2012Date of Patent: November 18, 2014Assignee: SK Hynix Inc.Inventors: Byeong Chan Choi, Gyung Tae Kim
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Publication number: 20130215697Abstract: A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.Type: ApplicationFiled: September 3, 2012Publication date: August 22, 2013Applicant: SK HYNIX INC.Inventors: Byeong Chan CHOI, Gyung Tae KIM
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Patent number: 8339885Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.Type: GrantFiled: December 16, 2010Date of Patent: December 25, 2012Assignee: SK Hynix Inc.Inventor: Byeong Chan Choi
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Publication number: 20120002492Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.Type: ApplicationFiled: December 16, 2010Publication date: January 5, 2012Applicant: Hynix Semiconductor Inc.Inventor: Byeong Chan CHOI
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Patent number: 8027205Abstract: A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response to the write strobe signal.Type: GrantFiled: June 23, 2009Date of Patent: September 27, 2011Assignee: Hynix Semiconductor Inc.Inventor: Byeong-Chan Choi
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Publication number: 20100165759Abstract: A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response to the write strobe signal.Type: ApplicationFiled: June 23, 2009Publication date: July 1, 2010Inventor: Byeong-Chan Choi