Abstract: A computing device and a driving method thereof are provided. The computing device is a computing device having a main board with a plurality of elements, and includes a linear regulator unit including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements and apply the different voltages, and a femto-clock generation unit including a plurality of femto-clock generators configured to generate femto-clocks of different frequencies to be used for control of operations of the plurality of elements.

Abstract: An MPEG video decoding system including: a buffer for storing an MPEG-formatted or a DV-formatted video signal; a VLD/IQ unit for performing a variable length decoding and an inverse quantization of the video signal; an IDCT device for selectively performing an 8×8 IDCT and a 4×8 IDCT according to the format of the inversely quantized signal; an adder for bypassing and storing the output signal of the IDCT unit into an external memory if the output signal of the IDCT unit is an MPEG-formatted I-picture or a DV format, and for adding the IDCT-ed signal and a motion compensated signal if the output signal of the IDCT device is an MPEG-formatted P-picture or B-picture; and a motion compensator for performing a motion compensation outputting the motion compensated signal to the adder, if the output signal of the IDCT device is the MPEG-formatted P-picture or the MPEG-formatted B-picture.

Abstract: A method and apparatus for decoding a bit stream encoded in a digital camcorder (DV) format is disclosed. The method includes a preprocessing step of detecting a position of an EOB (end of block) of respective DCT blocks using length information of a variable-length code of a bit stream encoded in the DV format, and a step of redefining a processing order of the DCT blocks according to the position of the EOB detected at the preprocessing step, and performing a variable-length decoding with respect to the respective DCT blocks in the redefined processing order. The blocks that can be processed are preferentially transmitted according to the detection of the EOB in transmitting the bit stream to the variable-length decoder, and thus the delay that may be produced when the whole block is sequentially processed can be minimized. Also, since the decoding is performed through redefining of the processing order of the DCT blocks, a storage device only for one DCT block can be used.

Abstract: This invention provides an MPEG video decoding system.

Abstract: A method and apparatus for decoding a bit stream encoded in a digital camcorder (DV) format is disclosed. The method includes a preprocessing step of detecting a position of an EOB (end of block) of respective DCT blocks using length information of a variable-length code of a bit stream encoded in the DV format, and a step of redefining a processing order of the DCT blocks according to the position of the EOB detected at the preprocessing step, and performing a variable-length decoding with respect to the respective DCT blocks in the redefined processing order. The blocks that can be processed are preferentially transmitted according to the detection of the EOB in transmitting the bit stream to the variable-length decoder, and thus the delay that may be produced when the whole block is sequentially processed can be minimized. Also, since the decoding is performed through redefining of the processing order of the DCT blocks, a storage device only for one DCT block can be used.