Abstract: A coil component includes a body, a supporting member disposed in the body and including one surface and the other surface opposing the one surface in a first direction, a first coil including a first winding portion disposed on one surface of the supporting member, a second coil including a second winding portion disposed on the other surface of the supporting member, a first external electrode and a second external electrode connected to one end and the other end of the first coil, respectively, a third external electrode and a fourth external electrode connected to one end and the other end of the second coil, respectively, and a first connection electrode and a second connection electrode disposed on the other surface side of the supporting member and connecting one end and the other end of the first coil to the first and second external electrodes, respectively.

Abstract: A coil component includes a body having a first surface, and a first end surface and a second end surface connected to the first surface and opposing each other in a length direction; a support substrate disposed inside the body; a coil portion comprising a first coil pattern and first and second lead-out patterns, each disposed on a first surface of the support substrate; first and second slit portions, respectively defined on edge portions of the first surface of the body to expose the first and second lead-out patterns; and first and second external electrodes disposed on the first and second slit portions to be connected to the first and second lead-out patterns. At least one of the first and second lead-out patterns has a thickness greater than a thickness of each of the first coil pattern and the first dummy lead-out pattern.

Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: An embodiment joint structure for a robot includes an upper plate provided in an upper region, a link part coupled to a lower surface of the upper plate, wherein the link part includes a first link and a second link, and wherein the first link and the second link are provided close to one side of the upper plate with respect to a center of the lower surface of the upper plate, a support part coupled to the lower surface of the upper plate and configured to support the upper plate, wherein the support part is provided to be closer to the center of the lower surface of the upper plate than is the link part, and a motor part configured to provide power to the support part and the link part.

Abstract: Provided are a method and apparatus for displaying a translucent image. An image display apparatus detects a plurality of voxels overlapping in a depth direction in three-dimensional (3D) image data, determines a first combination ratio for two colors based on transparency values of a first voxel and a second voxel, generates a first mixed color by combining a color of the first voxel with a color of the second voxel at the first combination ratio, and displays a mixed color on a screen.

Abstract: Disclosed is a test socket. The test socket includes a first block comprising a first base member of a conductive material and a first insulating member of an insulating material, a second block comprising a second base member of a conductive material and a second insulating member of an insulating material, a gap member of an insulating material, interposed between the first block and the second block, a first probe supported being in contact with the first base member and being not in contact with the second base member, a second probe supported being not in contact with the first base member and being in contact with the second base member, and electronic parts provided in the gap member and placed on a conductive path by which the first base member and the second base member are electrically connected.

Abstract: An embodiment joint structure for a robot includes an upper plate provided in an upper region, a link part coupled to a lower surface of the upper plate, wherein the link part includes a first link and a second link, and wherein the first link and the second link are provided close to one side of the upper plate with respect to a center of the lower surface of the upper plate, a support part coupled to the lower surface of the upper plate and configured to support the upper plate, wherein the support part is provided to be closer to the center of the lower surface of the upper plate than is the link part, and a motor part configured to provide power to the support part and the link part.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: A height adjustment module includes a mounting part extending on a plane; a plurality of support arms disposed around the mounting part on the plane on which the mounting part has been extended, and coupled to the mounting part to be rotatable upward or downward; a plurality of travelling parts each being coupled to a first end portion of the support arm, respectively, and including a wheel contacting the ground, respectively; a lift extending over the plane, and connected to second end portions of the plurality of support arms so that vertical movement is interlocked with each other; and a support link coupled to the mounting part to be vertically slidable, and coupled to the lift to be vertically fixed to move the mounting part relative to the lift as the support link is slid in the mounting part.

Abstract: A height adjustment module includes a mounting part extending on a plane; a plurality of support arms disposed around the mounting part on the plane on which the mounting part has been extended, and coupled to the mounting part to be rotatable upward or downward; a plurality of travelling parts each being coupled to a first end portion of the support arm, respectively, and including a wheel contacting the ground, respectively; a lift extending over the plane, and connected to second end portions of the plurality of support arms so that vertical movement is interlocked with each other; and a support link coupled to the mounting part to be vertically slidable, and coupled to the lift to be vertically fixed to move the mounting part relative to the lift as the support link is slid in the mounting part.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.