Abstract: The present disclosure provides a novel compound represented by the following Chemical Formula 1, and an organic light emitting device including the same: wherein A1 to A4, X, Y and n are described herein.

Abstract: An object of the present inventive concept is providing a nonvolatile memory device having improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device according to the present inventive concept includes a memory cell array connected to a plurality of word lines; and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to an unselect word line among the plurality of word lines when a read operation is performed. The voltage generator generates the unselect read voltage having a different level according to whether the unselect word line is adjacent to the select word line or not. A nonvolatile memory device according to the present inventive concept compensates a threshold voltage increased or decreased due to various causes. According to the present inventive concept, reliability of a nonvolatile memory device is improved.

Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

Abstract: An object of the present inventive concept is providing a nonvolatile memory device having improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device according to the present inventive concept includes a memory cell array connected to a plurality of word lines; and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to an unselect word line among the plurality of word lines when a read operation is performed. The voltage generator generates the unselect read voltage having a different level according to whether the unselect word line is adjacent to the select word line or not. A nonvolatile memory device according to the present inventive concept compensates a threshold voltage increased or decreased due to various causes. According to the present inventive concept, reliability of a nonvolatile memory device is improved.

Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

Abstract: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.

Abstract: Provided are an apparatus and method of protecting a user's privacy information and corporate intellectual property against a denial-of-information (DoI) attack, and more particularly, a privacy & intellectual property protection framework (PIPPF) and a network-based privacy & intellectual property protection system (NPIPPS). The PIPPF includes the NPIPPS and an integrated identity access and management (IAM)/network access control (NAC) solution. The NPIPPS monitors inbound and outbound contents at the network level and prevents the leakage of important information. In addition, the integrated IAM/NAC solution prevents abnormal user activity within a network and unauthorized use of information.

Abstract: User/service authentication methods and apparatuses using split user authentication keys are provided. A user authentication key is generated using user's personal information including an identification number and bio information, the generated user authentication key is split into a plurality of keys, and a request for authentication of a user that uses a first user authentication key provided to the user from among the plurality of split user authentication keys is authenticated using the other user authentication keys.

Abstract: A method for manufacturing a transflective LCD includes forming a gate line and a gate pad extending from the gate line on a substrate, forming an gate insulation layer over an entire surface of the substrate, forming a data line and a data pad extending from the data line, the data line crossing the gate line to define a unit pixel, forming a thin film transistor at the crossing of the gate line and the data line, forming a passivation layer over an entire surface of the substrate including the thin film transistor, patterning the passivation layer to form a plurality of contact holes each exposing a corresponding drain electrode, the gate pad, and the data pad of the thin film transistor, forming a transmissive electrode at a transmissive portion in the unit pixel region on the passivation layer, forming a reflective electrode at a reflective portion in the unit pixel region on the passivation layer, and forming an oxidation prevention layer including a transparent conductive film and a metal layer, wherein

Abstract: Disclosed herein is a system for providing media service using a sensor network and metadata. The sensor network includes a plurality of sensor network nodes connected to a media server and one or more media devices, respectively. The media server includes a media information storage unit, a sensor interface unit, a metadata storage unit, a content selection unit and a content transmission unit. The media device includes a content reception unit, a sensor interface unit and a metadata storage unit. The sensor network nodes each include a network interface unit, a device interface unit and a metadata storage unit. In detail, the metadata are input to the corresponding sensor network node, media content desired by a user is intelligently retrieved based on the metadata, and the media content desired by the user is provided to the media device desired by the user, including a mobile media device in the user's possession, at a time desired by the user.

Abstract: An apparatus and method for adaptively preventing attacks which can reduce false positives and negatives for abnormal traffic and can adaptively deal with unknown attacks are provided. The apparatus includes: a behavior analysis unit which estimates an attack detection critical value by analyzing the behavior of network traffic; a traffic determination unit which determines what type of traffic the network traffic is using the estimated attack detection critical value; an attack determination unit which determines whether the network traffic is abnormal by analyzing the network traffic according to a set of determination rules; and an adaptive attack prevention unit which handles the network traffic based on the determination results provided by the attack determination unit. Accordingly, it is possible to reduce false positives and negatives for abnormal traffic or unknown attacks input to a network.

Abstract: The provided method and system is a method and system for analyzing the malicious code protocol and generating harmful traffic. The harmful traffic generating method constructs packet protocol information for generating a first attack packet corresponding to the TCP/IP protocol for generating network traffic, and then sets network vulnerability scanning for generating a second attack packet for carrying out network vulnerability scanning. Subsequently, the method constructs attack information for generating a third attack packet in the form of denial of service, and generates harmful traffic using the packet protocol information, network vulnerability scanning and attack information. Accordingly, performance testing of the network security system against malicious code attacks such as the Internet worm can be performed.

Abstract: An apparatus and method for controlling abnormal traffic are provided.

Abstract: A panel conveying apparatus for a press line comprises a shuttle feeder and at least one panel position regulating device. The shuttle feeder is configured to be movable between presses. The panel position regulating device is mounted on the shuttle feeder and includes a panel guide unit, a rotating screw axis unit, and a link unit. The panel guide unit is configured to guide the panel. The rotating screw axis unit comprises a rotating screw axis and an actuator rotating the rotating screw axis. The link unit connects the panel guide unit and the rotating screw axis unit such that a vertical position of the panel guide unit is regulated in response to a rotation of the rotating screw axis.

Abstract: A mapping apparatus, and a method of controlling the same, including a cassette having a plurality of slots into which planar objects are inserted, and at least one reflector which reflects light beams irradiated into the plurality of slots; and a sensor unit having a light emitting unit and a light receiving unit, the sensor unit determining whether the planar objects have been inserted into the respective slots by determining whether a light beam, irradiated from the light emitting unit, is reflected from the reflector and then received by the light receiving unit.